In today's increasingly complex chip design and manufacturing landscape, testing technology faces unprecedented challenges. Achieving higher efficiency while maintaining testing accuracy has become a focal point across the entire semiconductor industry chain. As a technology pioneer, Advantest will showcase cutting-edge testing technologies and innovative solutions at the Siemens EDA Forum 2025 on August 28th, helping the industry collectively address next-generation intelligent chip challenges.

Meet Advantest Face-to-Face Time: August 28, 2025 (Thursday) Location: Shanghai JW Marriott Marquis Hotel (No. 988 Puming Road, Pudong New Area) Registration: Siemens EDA Forum 2025

Technical Expert Analysis Focusing on the forefront of testing technology, Advantest will deliver keynote presentations.

Manufacturing and Testing Track Collaboration between Advantest and Tessent in Advanced Testing Technologies Yan Zexin, Digital Business Development Manager, Advantest

Exhibition Highlights Preview Showcasing two core themes simultaneously, learn about testing solutions on-site.

V93000 EXA Scale High-Speed Scan Solution As high-performance chips adopt more complex designs and advanced packaging, the testing phase faces unprecedented technical challenges: exponential growth in test data volume, increased difficulty in multi-core parallel testing... These issues not only affect chip yield but may also drive up mass production costs and delay product launches.

The high-speed Scan testing solution jointly empowered by the Advantest V93000 EXA Scale platform and Siemens AG Tessent SSN architecture comprehensively improves Scan testing efficiency and accuracy during the chip mass production phase.

EXA Scale High-Speed Scan Solution Technical Highlights:

1. PS5000 Board 5Gbps High-Speed Capability Supports high-speed narrow bus (1.6Gbps to 3.2Gbps), significantly reducing test time.

2. Multi-Core Parallel Testing Support Supports both On-Tester Compare and On-Chip Compare testing modes, helping customers efficiently complete multi-core parallel, high-speed Scan validation.

3. Precise Fail Location and Analysis The platform can automatically collect Fail Cycles and complete core mapping with structured output. Flexible configuration enables per-core diagnostic capabilities, facilitating rapid diagnosis and debugging.

4. Compatible with Traditional DFT Processes, Building EDA and ATE Closed-Loop Collaboration Achieves efficient closed-loop between design and testing. Ensures SSN testing maintains compatibility with traditional DFT processes while operating at high speed and high concurrency, greatly simplifying collaborative work between design and testing.

SiConic Solution

SiConic Introduction Advantest SiConic: A scalable ecosystem supporting Design Verification and Silicon Validation teams in a unified, automated, and versatile environment, redefining Silicon Validation: seamless, scalable, and efficient solutions for today's SoCs.

From device bring-up to comprehensive data collection and analysis across different SoC/IP configurations, processes, and test conditions: SiConic ensures seamless and reliable Sign-Off pathways.

SiConic Functions Validation Solution: Bridge from EDA to actual chip testing Test Engineering Solution: Early DFT content verification through HSIO Comprehensive post-silicon validation environment enabling perfect setup, efficient data collection, and interactive analysis; supports high-bandwidth data transmission, control interfaces, and versatile Bench equipment for GPIO.

SiConic-Explorer: One-stop chip bring-up and validation tool SiConic-Link: Versatile, reliable Bench equipment for automated post-silicon validation

SiConic Four Key Highlights:

1. Plug-and-Play, Instant Debug Startup No lengthy data conversion required; DV and SV engineers can collaborate, reducing debug time from one day to one hour.

2. Real-time SoC/IP Configuration and Monitoring Supports dynamic on-chip configuration and behavior monitoring, quickly validating post-tapeout system functionality.

3. Data Visualization for Clearer Decision-Making Real-time chart generation and actionable data, intuitively presenting system status to guide team performance optimization.

4. Automated Test Sets with Comprehensive Coverage Supports data collection and analysis across multiple configurations and process scenarios, improving sign-off reliability while lowering cognitive barriers.