Semiconductor testing equipment provider Teradyne and Japanese semiconductor equipment giant Tokyo Electron announced a new integrated test cell solution on Monday, specifically designed for die yield screening in AI and data center applications.

This solution combines Teradyne's UltraFLEXplus test platform with Tokyo Electron's Prexa SDP single-die prober, providing a production-ready known-good-die screening path for advanced 2.5D and 3D packaging.

As AI and data center chip architectures increasingly adopt chiplet-based designs, integrating multiple dies into a single package, a single defective die can render an entire high-value package useless. Therefore, introducing known-good-die screening at multiple points in the packaging flow is critical for protecting final yield, improving quality, and maximizing output.

The president of Teradyne's Semiconductor Test division stated that AI device innovation is advancing at an unprecedented pace, and customers require reliable screening support at every stage of advanced packaging. The combination of Tokyo Electron's Prexa SDP and Teradyne's UltraFLEXplus provides customers with a production-ready solution that offers the temperature accuracy, power density, and digital performance required by today's AI and data center chips.

The integrated test cell can effectively manage the device temperature and high-power thermal characteristics of AI chips. Built on an open ecosystem architecture, it offers customers flexibility across compatible probe cards, handlers, and interface technologies, and can be integrated with other probers or testers as needed.

Teradyne and Tokyo Electron will demonstrate this technology at the SWTest conference, held at the Omni La Costa Resort in Carlsbad, California, from today through Wednesday. The solution is now commercially available and open to fabless design companies, wafer foundries, and outsourced semiconductor assembly and test providers.