Renowned analyst Ming-Chi Kuo offers a deep analysis of a recently leaked slide from TSMC concerning CoWoS glass substrates, concluding that the glass core substrate (the "oS" part) within the CoPoS packaging architecture is a fundamental requirement for the successful manufacturing of AI chips rather than a discretionary improvement, indicating the market significantly underestimates its strategic importance.

TSMC delivered a presentation titled "Advanced Packaging Technology Indispensable for AI Evolution" at the JPCA Show in Japan on June 11, 2026. A slide titled "CoWoS Glass Substrate Development" from this presentation subsequently circulated online, drawing extensive industry attention. In the presentation, TSMC formally announced its collaboration with Ibiden and Innolux to develop a glass core substrate, featuring a three-layer design—a glass core sandwiched between two ABF buildup layers, forming the "oS" in CoPoS.

Kuo highlights that the power integrity (PI) improvement data shown on the slide is the most commercially valuable information. The thinner nature of the glass substrate shortens the vertical conduction path through glass vias (TGV), simultaneously reducing conduction resistance and loop inductance. This leads to more stable power delivery, creating headroom for integrating more transistors or increasing clock speeds, ultimately translating directly into stronger AI computing power. This is the fundamental reason for the keen interest shown by NVIDIA and two other US customers in this technology.

According to Kuo's supply chain investigations, if progress proceeds smoothly, TSMC aims to commence mass production of the glass substrate between the fourth quarter of 2028 and the first quarter of 2029, aligning with the iteration cadence of NVIDIA's AI chips.

Tripartite Collaboration Overcomes Key Mechanical Structure Hurdle

TSMC's collaboration with Ibiden and Innolux has achieved critical progress in mechanical structure validation. Supply chain checks indicate the glass core substrate showcased in the slide is cut from entire 250x250mm panels. The ABF buildup layers primarily use Ajinomoto's GL107, a hybrid ABF-GCP, with a tested layer count of 24 to 28 layers, which also represents the mainstream ABF specification for AI chips from 2027 to 2028.

In its experiments, TSMC used Chip-on-Wafer (CoW) as a test vehicle, pairing it with the "oS" glass core substrate for validation. This setup was sufficient to replicate the most challenging mechanical structure issues in composite material processing. Kuo believes the positive test results signify that the three parties have jointly overcome a key technological bottleneck.

Regarding the division of labor, Ibiden is currently responsible for cutting the 250x250mm glass substrates. Kuo's investigation notes that a pre-mass production simulation phase for 510x515mm specifications is expected in the second half of 2027. At that point, if Ibiden wishes to reduce production complexity to protect its ultra-high gross margins, it may transfer the cutting process to Innolux, which has greater familiarity with glass properties.

Essential vs. Optional: The Distinct Roles of oS and CoP

Kuo makes a clear distinction between the functional roles of the two core components in the CoPoS system. CoP addresses production efficiency and dicing yield economics, impacting cost and price; whereas oS addresses warpage and durability issues, determining whether a chip can be manufactured and function properly at all.

He further points out that CoP is a "very-nice-to-have" optimization; its absence means higher chip costs, but chips can still be made. In contrast, oS is a "must-have"; without it, the very feasibility of successful chip manufacturing is in question. This explains why TSMC chose to validate oS with the existing CoW test vehicle rather than with CoP—prioritizing verification of the most critical technical link.

Kuo specifically clarifies a common misinterpretation: the "COP" on the slide does not stand for Chip-on-Package but refers to Coplanarity, a technical metric measuring structural flatness.

Power Integrity Improvement: The Key Driver of Customer Willingness to Pay

Kuo describes the PI improvement data shown on the slide as the "real gold," explaining it from a customer payment logic perspective: Production efficiency is part of TSMC's fundamental responsibility, and customers will not pay extra for it. However, improvements in AI computing power directly relate to a customer's own competitiveness and profitability, making them willing to pay for such enhancements. This is the core reason for NVIDIA's highly positive stance on glass substrates.

For TSMC, glass substrates, while improving packaging yield and reducing costs, also elevate the computing power and selling price of AI chips, delivering both cost-reduction and price-premium effects, which positively impact profitability and competitive positioning.

Furthermore, during the Q&A session following the presentation, when an attendee inquired about TGV details for the glass substrate, TSMC declined to answer on the spot. Kuo views this stance itself as a signal—TGV is a core, key technology of the glass substrate, with related core intellectual property currently jointly held by TSMC and Innolux, which TSMC is unwilling to disclose publicly. In contrast, when another attendee asked about integration schemes for IVR, eDTC, and LSI, TSMC provided a detailed response.

Cost Structure: High Unit Price Unlikely to Deter Adoption

The unit price of glass substrates is several times higher than that of current ABF substrates, with the glass processed by Innolux being the most critical and expensive single material. Despite this, Kuo believes the high unit price will not substantially suppress customer adoption willingness.

The reason lies in the overall cost structure: Substrate cost currently accounts for only a low single-digit percentage of an AI chip's bill of materials (BOM), while packaging yield loss is approximately 5 to 10 times the cost of the substrate. Therefore, even if the glass substrate cost is several times higher than today's, its proportion within the BOM remains relatively low. Simultaneously, it effectively reduces the larger costs associated with packaging yield loss. Overall, the economic case for customers to adopt glass substrates still holds.

Mass Production Targeted for Late 2028, Ibiden Roadmap Shows Deviations

Based on Kuo's supply chain investigations, if progress proceeds smoothly, TSMC aims to commence glass substrate mass production between the fourth quarter of 2028 and the first quarter of 2029, aligning with the iteration cadence of NVIDIA's AI chips.

A widely circulated slide from Ibiden's financial presentation marks the glass substrate mass production timeline as 2030. Kuo's interpretation is that Ibiden has historically been conservative and cautious in public communications; its formal inclusion of the glass substrate in its roadmap further confirms the long-term development trend of this technology. However, he simultaneously notes that some details in Ibiden's slide diverge from known market information—its photomask timeline differs by about one generation from TSMC's public statements, and the Rubin Ultra substrate size is also significantly larger than the 90x90 specification marked for 2026–2027 on the slide. He advises investors to cross-verify information from multiple sources when forecasting future trends and not to rely on a single source.