Recent reports suggest Alphabet's Google may be in discussions with Samsung Electronics to manufacture certain hardware components for its AI-focused Tensor Processing Units (TPUs). This development highlights the significant strain on the advanced manufacturing and packaging capacity of Taiwan Semiconductor Manufacturing (TSM), the world's leading chip foundry.

Furthermore, as TSMC's CoPoS advanced packaging system—which aims to push high-performance AI chip packaging from wafer-level to panel-level large-scale formats—potentially moves toward volume production by 2028, CoPoS could become the most critical growth driver for TSMC's advanced packaging business. This perspective challenges the simplistic market view that narrowing CoWoS capacity and supply-demand gaps equates to a loosening of AI computing power bottlenecks. It does not deny the phased improvement in CoWoS but points to a large-scale upgrade and migration of AI computing infrastructure constraints.

From an analytical standpoint, the narrowing of the CoWoS gap from 20% to an estimated 10% by late 2026 suggests marginal easing in the tightest phase of supply and demand for the current generation of AI chip advanced packaging. However, this does not imply a comprehensive removal of bottlenecks across the AI computing power supply chain. TSMC's latest capacity planning for CoPoS further indicates that the next phase of infrastructure bottlenecks is likely to shift from "Is there enough CoWoS capacity?" to "Can ultra-large AI chips achieve mass production with acceptable yield and cost using CoPoS advanced packaging?"

Industry analyst Ming-Chi Kuo has noted that TSMC's CoPoS is expected to enter volume production in the second half of 2028, aiming to improve the mass production economics for ultra-large AI packages exceeding 9.5x the reticle size, with Nvidia's potential Feynman AI GPU architecture being among the first adopters. This suggests TSMC is paving the way for larger chips, higher HBM stacks, and more complex chiplet-based heterogeneous integration in the post-Rubin Ultra/Feynman GPU era.

If the narrowing CoWoS gap represents short-term supply improvement, the CoPoS roadmap represents a long-term trend of upgrading AI computing infrastructure bottlenecks. From a broader market view, supply-side scarcity related to the AI computing chain is not diminishing but is transitioning from the logic of CoWoS capacity expansion to a new round of pricing for scarcity involving advanced node price increases, next-generation CoPoS large-scale packaging, glass core substrates, TGV (Through Glass Vias), ABF (Ajinomoto Build-up Film) substrate coexistence structures, and system-level yield economics.

TSMC's Capacity Strain Remains a Key Constraint

Analysts at Wedbush Securities have stated that reports of Google potentially negotiating with Samsung for TPU component manufacturing primarily underscore that TSMC's manufacturing and packaging capacity remains extremely tight, rather than indicating a loosening of advanced packaging bottlenecks for AI infrastructure as some media have suggested.

The firm argues that using an alternative foundry and splitting the advanced node chip manufacturing process would introduce additional complexity, likely negatively impacting yields and ultimately increasing chip tape-out or manufacturing costs, even if the TSMC alternative were cheaper. While acknowledging Samsung's improved position in the 3nm and below advanced foundry space, Wedbush notes that many of Samsung's recent wins appear qualitatively less significant, partly attributing this to special treatment and pricing for Tesla.

Discussions regarding the Samsung-Google foundry dynamic are not yet finalized. Under the reported arrangement, Samsung would manufacture the memory I/O die for the Google TPU, codenamed Icefish. The core computing engine of the TPU would reportedly continue to be manufactured and packaged by TSMC, where Google has historically produced its multi-generational TPU AI chips. Media reports citing sources indicate TSMC would use its most advanced 1.4nm-class process to produce this computing engine. This next-generation Google TPU could enter mass production as early as 2028, though timelines may change.

Reports also suggest Google is collaborating with MediaTek on the design of its eighth-generation TPU and the complementary Icefish design, with chip giant Broadcom also expected to participate in the full chip design, as it has with previous Google TPU generations. The TPU 8t (designed for training large AI models) and TPU 8i (designed for massive-scale AI inference) were officially unveiled in April at the Google Cloud Next 2026 event.

Advanced Node Price Hikes and CoPoS Launch New Pricing Cycle

The core advantage of CoPoS over CoWoS lies in its attempt to push AI chip packaging from wafer-level to panel-level large-scale formats. This addresses the pressure CoWoS faces in terms of area, cost, yield, and production economics when next-generation AI chips exceed reticle size limits. Traditional CoWoS relies on wafer-level silicon interposers, suitable for current GPU+HBM high-density interconnects. However, as AI package sizes expand to 9.5x the reticle size or larger, silicon interposer area, yield, and cost become bottlenecks.

CoPoS, through panel-level processes, glass core substrates, ABF buildup layers, TGV, and RDL (Redistribution Layer) structures, scales interconnect and load-bearing capacity to larger package sizes. Analyst Ming-Chi Kuo explicitly stated CoPoS targets volume production in the second half of 2028 to improve the mass production economics for ultra-large packages above 9.5x reticle size, with Nvidia's Feynman architecture a potential first adopter. He clarified that glass is not a "glass interposer" nor a replacement for ABF, but a three-layer structure with a glass core coexisting with upper and lower ABF buildup layers.

Therefore, CoPoS is likely to become a core incremental factor for TSMC's advanced packaging business post-2028, not by replacing CoWoS in the short term, but by ushering in a dual-track growth phase: continued CoWoS volume expansion alongside CoPoS accommodating ultra-large AI chips.

Google's potential move to have Samsung manufacture the memory I/O die for its TPU while keeping the computing engine at TSMC reinforces the view that this is not a breach of TSMC's moat nor a loosening of AI infrastructure packaging bottlenecks. Instead, it indicates that excessive tightness in TSMC's advanced node and CoWoS advanced packaging capacity is forcing major customers to explore splitting the manufacturing process and seeking second sources.

However, such splits increase challenges in design verification, packaging coordination, yield ramp-up, and cost control. Thus, it is not inherently positive for Samsung and negative for TSMC, but rather signals that demand for AI ASICs is so strong that even hyperscale customers like Google must "compete for capacity, share risk, and secure supply" in advanced nodes and packaging.

Rumors of TSMC price hikes up to 15%, the CoPoS roadmap, and the Google supply diversification reports are essentially different facets of the same issue: the real bottlenecks in the AI computing chain are expanding from single GPU supply to encompass advanced nodes, advanced packaging, HBM interconnects, ABF/glass substrates, TGV processes, and capacity allocation power.

Supply chain sources cited by TrendForce indicate TSMC's 3nm advanced node prices may increase by up to 15% in the second half of 2026, with potential further increases of 5-10% in 2027. The core driver is the explosive, sustained demand for AI ASICs and AI GPUs, pushing advanced node and packaging capacity to its limits. TSMC's CFO recently acknowledged inflationary and operational cost pressures while denying "four- or five-fold" price increases. This suggests the pricing adjustments are more akin to a "value repricing of bottleneck capacity in AI infrastructure chip manufacturing and advanced packaging" rather than short-term speculative spikes.

ASML's latest forecasts have significantly bolstered the long-term bull case for the global AI computing chain. Demand from AI data centers, Starlink satellites, embodied AI robots, autonomous driving, and future TeraFab-level super chip fabs will expand chip demand from pure cloud training to encompass broader cloud AI inference systems, physical AI, and edge AI cloud connectivity needs. This provides long-term, strong fundamental expansion logic for global chip leaders including ASML, TSMC, SK Hynix, Micron, Nvidia, AMD, Intel, Applied Materials, and Lam Research.

ASML's CEO has predicted the global semiconductor market could reach a staggering $1.5 trillion by 2030, compared to a market size of approximately $800 billion as of 2025.

TSMC's Stock Rally Shows No Signs of Slowing

Year-to-date, TSMC's US-listed ADRs have surged approximately 45%, building on a 340% gain since 2024. However, Wall Street analysts believe the rally is far from over. As of Monday's market open, TSMC ADRs traded around $435, with a market capitalization of approximately $2.26 trillion.

Recent Wall Street target prices compiled by TipRanks show a 12-month average price target of $465 from six analysts, with a high target of $500. This implies the most optimistic targets project TSMC's market cap toward the $2.6 trillion range, while the more aggressive average target corresponds to about $2.4 trillion. This indicates the market is already repricing TSMC from a "leading foundry" to a global core bottleneck asset in AI computing manufacturing infrastructure.

Analysts at Bank of America view AI computing infrastructure as entering a more durable and broader capital expenditure cycle. Almost simultaneously, a report from Morgan Stanley indicates the AI computing arms race is entering a system-level expansion phase, with AI infrastructure demand showing a rare "inelastic" trend—where tech giants continue to ramp data center construction regardless of the cost curve.

This "demand inelasticity" is expected to persistently strengthen US economic resilience and S&P 500 earnings growth. Morgan Stanley predicts that by 2028, nearly $3 trillion in AI-related infrastructure investment will flow through the global economy, with over 80% of that spending still ahead.

TSMC's CEO stated at the annual shareholder meeting in early June that demand will outstrip supply for many years to come, and even with new US capacity coming online, TSMC will struggle to fully meet AI-driven demand for several years. Regarding the AI capital expenditure outlook, his comments that "I don't know where the peak is" and "we have not seen any indicators of demand stopping" were perhaps the most bullish statements from a supply chain giant at the meeting regarding the AI computing chain.

Morgan Stanley has significantly revised its 2026 capital expenditure expectations for US tech giants upward from $433 billion a year ago to $805 billion. For 2027, capex is expected to reach $1.1 trillion, up from a previous forecast of $950 billion. This latest projection underscores that supply chain bottlenecks at the AI infrastructure level have expanded from "mass purchasing of GPUs/ASICs" to "striving to simultaneously solve the entire AI data center delivery chain," encompassing data center power equipment, liquid cooling, data center CPUs, DRAM/NAND/HBM, optical communication/interconnects, high-performance network interconnects, transformers, and gas turbines.