In recent years, Taiwan Semiconductor Manufacturing (TSMC) has not only actively invested in advanced process nodes to maintain its competitive edge but has also steadily increased its investment in packaging technology to meet the demands of next-generation artificial intelligence (AI) and high-performance computing (HPC) chips. The company has prepared a new generation CoPoS (Chip-on-Panel-on-Substrate) packaging technology that can expand substrates to 310 × 310 mm or even larger dimensions.

Taiwan Semiconductor Manufacturing is preparing to change its advanced packaging strategy by "panelizing" CoWoS technology, integrating it with Fan-Out Panel Level Packaging (FOPLP) technology to transition to CoPoS packaging technology. The company plans to adopt square substrates to replace the previous round substrates, which can effectively increase production capacity.

Taiwan Semiconductor Manufacturing plans to establish its first CoPoS packaging production line as early as 2026 for pilot production, with the responsible facilities being P4 and P5 at the AP7 facility in Chiayi, Taiwan. Mass production is expected to begin by the end of 2028 to the first half of 2029, with CoPoS projected to replace CoWoS-L in the future. The company has largely finalized the suppliers for the first batch of equipment and established relevant specifications and order quantities.

Like FOPLP, CoPoS also uses large panel substrates for packaging, but there are some differences between the two technologies. FOPLP is a packaging method that does not require an interposer layer, where chips are directly redistributed on panel substrates and interconnected through redistribution layers (RDL). This method offers advantages such as low cost, high I/O density, and flexible form factors, making it suitable for applications like edge AI, mobile devices, and mid-range ASICs with moderate integration density.

CoPoS introduces an interposer layer, providing higher signal integrity and stable power transmission, making it more effective for high-end products integrating GPU and HBM chips. Additionally, the interposer layer material is transitioning from traditional silicon to glass, which will provide higher cost-effectiveness and thermal stability.