Taiwan Semiconductor Manufacturing's (TSM) earnings report delivered the most substantial endorsement yet for the artificial intelligence industry. Its Q4 2025 financial results significantly surpassed expectations across multiple metrics, with revenue growing year-over-year for the eighth consecutive quarter, seemingly indifferent to industry cycles; its gross margin soared past 60%, rivaling software giants and drawing envious glances from manufacturing peers, leaving Samsung gnashing its teeth and Tesla green with envy.

What truly excited investment institutions was the capital expenditure. TSM provided guidance for 2026 capital expenditure of $52 to $56 billion, a substantial increase from the $40.9 billion spent for the full year 2025, offering a strong vote of confidence for the industry. As a chip foundry, TSM's capital expenditure is primarily used for building production lines and purchasing equipment. Capacity construction typically takes 2-3 years before it becomes operational, therefore TSM's level of capital spending essentially represents the future order growth from chip design companies like Nvidia and AMD. Furthermore, although TSM operates in the high-tech sector, it is a relatively conservative company in its operations. Following a 35% surge in capital expenditure in 2025, TSM signaling "significantly increased capital expenditure over the next three years" naturally delighted Wall Street.

Following the earnings call, not only did TSM's own stock price hit a new all-time high, but associated companies like Lam Research and Applied Materials also surged overnight, with its close partner ASML's market capitalization breaking through the $500 billion mark. Major institutions in both China and the US issued a flurry of research reports, with "certainty" becoming a frequently used term. If there is an AI bubble, it appears it can continue to inflate for several more years. Invincibility is Lonely TSM's current dominant position rests on two key pillars: 3nm process technology and advanced packaging. According to the financial report, revenue from the 3nm process accounted for a record-high 28% of TSM's Q4 revenue, exceeding 20% for the sixth consecutive quarter, driving the average selling price of wafers to grow by 20% for two consecutive years and serving as the primary contributor to its astonishing 62.3% gross margin.

The extraordinary profit-generating capability of the 3nm process is quite rare compared to any previous process node. Chip foundry is an industry perpetually focused on being first to market; the exclusivity of technology is the sole path to high margins. For a foundry, the time gap between launching a new process generation and competitors catching up to offer equivalent technology is the golden window for capturing supernormal profits. In 2014, TSM was the first to mass-produce 20nm, securing orders for Apple's A8 chip and seeing its gross margin rise accordingly. A year later, Samsung overtook it by skipping 20nm and launching 14nm first, forcing TSM to respond with price cuts, causing its gross margin to drop. Another six months later, TSM introduced its equivalent 16nm process, turning the tables and forcing Samsung to lower prices. In this back-and-forth race, the high-margin window for each process generation typically struggles to exceed two years. Yet for TSM's 3nm process, which entered mass production in Q3 2023, by Q4 2025—ten quarters later—the gross margin has increased instead of declined, primarily due to two major shifts. The first is the explosive surge in demand for AI compute chips. TSM's primary customers for advanced processes have traditionally been mobile chip companies like Apple and Qualcomm, as smartphones are highly sensitive to power consumption, creating a more urgent need for advanced processes. Conversely, GPUs from Nvidia and AMD were typically manufactured on processes one or two generations behind the leading edge. For example, the 2018 RTX 20 series used 12nm, not the most advanced 7nm available at the time. However, starting with the H100, Nvidia's adoption of advanced processes for its compute chips accelerated dramatically. The Vera Rubin GPUs scheduled for shipment in the second half of next year will utilize the N3P process, the best version currently available in TSM's 3nm family. This has led to a severe shortage of the 3nm capacity initially earmarked for customers like Apple, with reports this month indicating TSM has stopped accepting new 3nm orders, as capacity for the next two years is already fully booked [1]. The second factor is the underperformance of competitors. Before the 7nm era, TSM, Samsung, and Intel were relatively evenly matched; when one introduced a new process, the other two would catch up within a year or so. Post-7nm, however, no competitor has proven capable of challenging TSM. On paper, Samsung has mass-produced 3nm, but its performance and yield have not met the expectations of top-tier clients, currently relying mainly on its own mobile division to absorb output. Intel's roadmap extends to 1.4nm, but news of mass production remains elusive. The urgent demand and irreplaceable capability have endowed TSM with unprecedented pricing power. During the earnings call, CEO C.C. Wei was evasive on questions about further price increases, stating "many factors contribute to price increases," leaving the implications to be read between the lines. With the 3nm process facing no significant competition, advanced packaging provides a double insurance policy for TSM's "invincibility." Advanced packaging is one of the most important legacies from the era of founder Morris Chang, initially conceived to solve transmission rate bottlenecks between chip dies, which can be simply understood as "chip拼接" (piecing together chips). TSM established its advanced packaging department in 2008, and the now highly popular CoWoS packaging solution was completed as early as 2011. However, due to high costs, CoWoS remained relatively niche during the smartphone era but has shone brilliantly in the age of compute chips. Nvidia's H100 is formed by "piecing together" one GPU die with six HBM dies, and the B200 is directly formed by combining two B100 dies into a single unit. The philosophy for mobile chips is "making them smaller," whereas for AI compute chips, it's "piecing them together to make them larger"; the larger the chip, the greater the compute power, and the more dies involved, the greater the need for advanced packaging.

Nvidia's B200 is formed by combining two B100 dies. In the field of advanced packaging, competitors' performance has also been lackluster. Intel's EMIB didn't enter mass production until 2017, and Samsung's I-Cube, X-Cube, and other solutions were launched after 2018. At last year's mid-year GTC AI conference, Jensen Huang explicitly stated that there is currently no alternative to CoWoS [2]. CoWoS capacity has been tight from last year into this year, effectively gripping the main artery of AI chip supply. According to reports, TSM's current CoWoS capacity of 1.15 million units has been completely allocated among major players, with Nvidia taking 60%, AMD securing 8%, and the remainder contracted by Broadcom and MediaTek (which fulfills orders for Google, Meta, OpenAI) [3]. The proportion of advanced packaging within TSM's capital expenditure has also increased from around 8% historically to 10%-20% [4].

It is foreseeable that TSM's near-monopolistic position in both advanced processes and advanced packaging will persist for a considerable time. From Big A to Big N Last November, Jensen Huang made a quick visit to TSM's Fab 18 in the Southern Taiwan Science Park, inspecting the 3nm production lines and even finding time to participate in TSM's sports day. According to TSM Chairman C.C. Wei, Huang's visit was to "ask for more chips" [5]. Well-known analyst Ming-Chi Kuo added a detail: Huang pointed to the land adjacent to Fab 18 and expressed willingness to purchase it to secure part of the capacity that was not yet allocated.

The highly profitable AI compute chips have helped TSM solve a major problem: a lack of customers for its advanced processes. As chip processes entered the deep waters below 10nm, R&D costs and risks increased rapidly, creating a heavy reliance on certainty from downstream orders, making deep partnerships with major clients crucial. On one hand, confirmed orders ensure sufficient R&D investment and risk sharing; on the other hand, collaborating with clients early in the R&D phase enhances the success rate of technology implementation. TSM's collaboration with Apple began with the mass production of the A8 chip in 2013. TSM invested $10 billion to develop the then-unproven 20nm technology, making its name with this endeavor. Since then, the yield improvement for each of TSM's processes has benefited from Apple's support. However, during the initial rollout of the 3nm process, due to low yields (initially below 60%) and high scrap costs, Apple, as the sole 3nm customer, was reportedly pressuring TSM to reduce wafer prices from $20,000 per wafer to $16,000-$17,000, charging based on "usable qualified wafers" and having TSM bear the losses from defective wafers. This wasn't merely Apple being stingy; the cost of 3nm was simply too high for Apple to shoulder alone. Unexpectedly, in 2024, AI compute demand exploded completely. Coupled with TSM's launch of the N3E platform specifically designed for AI acceleration, AI chip companies led by Nvidia flooded the demand side, queuing for capacity stretching into 2026 [6]. In the middle of last year, then TSM co-COO Y.J. Mii confirmed that collaboration with Nvidia had escalated from design and process to system-level integration [7]. More recently, rumors suggest that Nvidia has become the first and only customer for TSM's A16 (equivalent to 1.6nm) process, with joint testing already formally underway [8]. If these reports are accurate, this would mark the first time Apple has been absent from the development of a new TSM process since the 20nm era, with Nvidia taking over Apple's role as TSM's new "technology sponsor." According to analysis by Culpium incorporating supply chain information, while Apple remains TSM's largest customer in 2025, Nvidia has already become the largest customer on a single-quarter basis. It is projected that in 2026, Nvidia will formally surpass Apple to become the "Big A" among TSM's major customers [9].

TSM and Nvidia have produced the first Nvidia Blackwell chip wafers in the United States. Shortly after TSM's 2nm process entered mass production at the end of last year, media reports claimed its 2026 capacity had already been fully booked by various manufacturers, a stark contrast to the initial predicament of the 3nm process having only Apple as a customer. According to statements made during TSM's earnings call, the initial revenue scale of the 2nm process is expected to exceed that of the 3nm process. TSM's capital expenditure, which greatly exceeded expectations, is also a result of surging orders from downstream chip companies. The lead time from breaking ground on chip capacity to production varies from 2 to 3 years, meaning that the $56 billion capital expenditure guidance for 2026 represents TSM's forecast for demand two years hence. This is based on the unanimous feedback TSM received during its customer due diligence: "Only TSM's chips are the bottleneck; don't worry about anything else [4]." According to its plans, 70%-80% of TSM's capital expenditure will be allocated to advanced processes, 10% to advanced packaging, and its revenue compound annual growth rate from 2024 to 2029 is projected to reach an astonishing 25%. For competitors, facing such an invincible TSM, relying solely on money means this battle is already effectively unwinnable.