Cadence Design Systems Expands Partnership with TSMC to Advance AI and HPC Chip Design Using Next-Gen Automation and IP Solutions

Reuters

09/25

Cadence Design Systems Expands Partnership with TSMC to Advance AI and HPC Chip Design Using Next-Gen Automation and IP Solutions

Cadence Design Systems Inc. has announced significant advancements in chip design automation and intellectual property $(IP)$ through its close collaboration with TSMC. The partnership focuses on developing advanced design infrastructure and accelerating time to market for AI and high-performance computing (HPC) applications. Cadence's AI-driven electronic design automation (EDA) solutions and IP are now available for TSMC's latest process nodes, including N3, N2, and A16, as well as for TSMC's 3DFabric technology. The two companies are also working together on EDA flow development for TSMC's forthcoming A14 process. This ongoing collaboration empowers customers to enhance design performance and energy efficiency, streamlining the journey from concept to silicon in the fast-evolving AI semiconductor landscape.

Disclaimer: This news brief was created by Public Technologies (PUBT) using generative artificial intelligence. While PUBT strives to provide accurate and timely information, this AI-generated content is for informational purposes only and should not be interpreted as financial, investment, or legal advice. Cadence Design Systems Inc. published the original content used to generate this news brief via Business Wire (Ref. ID: 20250924566415) on September 24, 2025, and is solely responsible for the information contained therein.

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The partnership focuses on developing advanced design infrastructure and accelerating time to market for AI and high-performance computing (HPC) applications. Cadence's AI-driven electronic design automation (EDA) solutions and IP are now available for TSMC's latest process nodes, including N3, N2, and A16, as well as for TSMC's 3DFabric technology. The two companies are also working together on EDA flow development for TSMC's forthcoming A14 process. This ongoing collaboration empowers customers to enhance design performance and energy efficiency, streamlining the journey from concept to silicon in the fast-evolving AI semiconductor landscape.\n      </p>\n</div><div xmlns:xsd=\"http://www.w3.org/2001/XMLSchema\" xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\">\n<em>Disclaimer: <span>This news brief was created by Public Technologies (PUBT) using generative artificial intelligence. While PUBT strives to provide accurate and timely information, this AI-generated content is for informational purposes only and should not be interpreted as financial, investment, or legal advice. Cadence Design Systems Inc. published the original content used to generate this news brief via Business Wire (Ref. ID: 20250924566415) on September 24, 2025, and is solely responsible for the information contained therein.</span></em>\n</div></body></html>\n\n</article>\n</div>\n</body>\n</html>\n","isBrief":false,"type":0,"news_type":1,"symbol":"IE00BN0W2V16.EUR","symbol_name":"GUINNESS SUSTAINABLE GLOBAL EQUITY \"C\" (EUR) ACC","start_time":0,"source_url":"https://api.refinitiv.com/data/news/v1/stories/urn:newsml:reuters.com:20250924:nNDL75Z3gp:1","article_id":"2570080156","we_media_id":"1032215980","thumbnails":[],"rights":null,"url":"https://stock-news.laohu8.com/highlight/detail?id=2570080156","pubTimestamp":1758744925,"columns":[],"sourceInfo":null,"weMediaInfo":{"media_name":"Reuters","introduction":"Reuters.com brings you the latest news from around the world, covering breaking news in markets, business, politics, entertainment and technology","home_visible":1,"id":"1032215980","head_image":"https://community-static.tradeup.com/news/4567337cbdf294b657b1fa87c5488b48"},"summary":"Cadence Design Systems Expands Partnership with TSMC to Advance AI and HPC Chip Design Using Next-Gen Automation and IP Solutions. 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