TradingKey - On July 30, Eastern Time, according to a report by The Information, TSMC ( TSM) is developing an advanced packaging technology to rival Intel's ( INTC) EMIB, internally referred to as "EMIB-like". Following the news, TSMC's US ADR surged 7.64% on Thursday to close at $403.31.
During the Asian trading session on July 31, boosted by both the overnight surge in TSMC's ADR and Microsoft's better-than-expected earnings that ignited confidence in AI investments, TSMC's Taiwan-listed shares opened with a massive gap up, hitting the daily limit-up of NT$2,425 (approximately $74.8) during intraday trading, representing a gain of 9.98%.
[Source: TradingView]
Chip packaging is the final step in semiconductor manufacturing, traditionally viewed as a relatively standardized back-end process. However, as AI chips continue to advance toward higher computing power and greater bandwidth, requiring the integration of multiple GPUs, CPUs, and High Bandwidth Memory (HBM) within a single package, advanced packaging has become one of the most critical capacity bottlenecks in the AI supply chain.
TSMC President C.C. Wei previously admitted that CoWoS capacity is "extremely tight, which has limited customers' business expansion," with advanced node and packaging capacity already fully booked through 2027.
Against this backdrop, Intel's EMIB (Embedded Multi-die Interconnect Bridge) technology has garnered market attention. Unlike CoWoS, which relies on a large silicon interposer, EMIB achieves high-speed interconnection by embedding micro silicon bridges at the edges of the dies, eliminating the need for a full silicon interposer. Consequently, it theoretically offers lower packaging costs, higher area utilization, and the ability to support larger-scale heterogeneous chip integration.
According to reports, Google ( GOOGL) has planned to commission Intel to produce over 3 million TPUs, while Nvidia ( NVDA) is also evaluating whether to adopt the EMIB solution.
In the face of competition from EMIB, TSMC's development of an "EMIB-like" technology aims to both alleviate the pressure from long-term CoWoS capacity constraints and capture a broader share of the advanced packaging market. If this solution is successfully implemented, TSMC will add a lower-cost, more widely applicable packaging route alongside CoWoS, providing customers with more choices and reducing dependence on a single packaging architecture.
According to people familiar with the matter, TSMC is currently cooperating with Taiwanese chip substrate manufacturer Kinsus Interconnect Technology. Within this division of labor, Kinsus will be responsible for the design, testing, and manufacturing of the advanced substrates that house the micro silicon bridges.
However, challenges remain. Intel has been positioning its EMIB technology for years, and it has already entered the adoption phase for some customers. TSMC's EMIB-like technology is still in the early stages of R&D, and once customers choose a packaging route, the switching costs later on are extremely high.
Amid the AI wave, advanced packaging is advancing along two technical routes simultaneously. CoWoS continues to serve flagship training chips, while the EMIB route fills the demand for more cost-sensitive and larger packaging areas. Whether TSMC can capture more market share from Intel depends on the speed of its technological progress and customers' willingness to adopt it.
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