Taiwan Semiconductor Manufacturing has reached a key milestone in its advanced process technology roadmap. According to industry sources cited by a Taiwanese media outlet, the company has completed the development and verification of its A16 process and plans to enter mass production in the fourth quarter of this year.

As the first angstrom-level CMOS platform from Taiwan Semiconductor Manufacturing to utilize the "Super Power Rail" backside power delivery architecture, A16 is specifically designed for applications requiring extreme compute performance, energy efficiency, and power stability, such as AI accelerators and high-performance computing chips.

Compared with the previous N2P process, A16 delivers an 8% to 10% performance improvement at the same power consumption, or a 15% to 20% reduction in power draw at equivalent performance levels, alongside an 8% to 10% increase in transistor density. Its primary advantage extends beyond backside power delivery; it also minimizes changes to the front-side transistor structure and existing design ecosystem.

Backside power delivery tackles wiring bottlenecks in advanced processes

As process nodes continue to shrink, the traditional front side of a chip must handle both power delivery and signal interconnects. The limited wiring space increasingly falls short of the demands of high-performance computing chips, exacerbating issues such as line congestion and IR drop (resistance-induced voltage drop).

The concept of backside power delivery is to relocate the power network from the front side of the chip to the backside, freeing up front-side wiring resources for signal interconnects while reducing resistance and voltage drop along the power path. However, this technology is not simply a matter of "moving power to the back." Backside power delivery typically requires adjustments to transistors, standard cells, and even the entire design flow, potentially imposing significant IP reconfiguration and design migration costs on customers.

The A16 process from Taiwan Semiconductor Manufacturing employs dedicated vertical backside contacts (VB) to connect power directly to the source and drain of transistors, enabling the separation of the power network from the signal network. More critically, the company aims to keep front-side modifications to a minimum. A16 retains the gate density and NanoFlex design flexibility of N2P, enhancing power efficiency while preserving compatibility with the existing chip design ecosystem.

This means that for customers already designing on Taiwan Semiconductor Manufacturing's advanced processes, migrating to A16 may not require large-scale reconstruction of standard cells or design architectures. This advantage is particularly significant for AI accelerators and high-performance computing chips, which typically have long design cycles and high IP complexity.

Rising AI compute demand accelerates advanced process evolution

The introduction of A16 is driven by the heightened requirements that AI chips place on advanced manufacturing. AI accelerators and high-performance computing chips integrate a vast number of compute units, demanding far greater power integrity, signal routing, and energy efficiency than conventional chips. Backside power delivery, by freeing up front-side wiring resources and improving power efficiency, is widely regarded as a critical technical pathway for further enhancing AI chip performance and energy efficiency.

If A16 enters mass production as planned in the fourth quarter of this year, Taiwan Semiconductor Manufacturing will be the first to accumulate large-scale production experience with backside power delivery. As AI compute demand continues to grow, whether A16 can win over customers with its combined strengths in performance, energy efficiency, and design compatibility will serve as a key indicator of the company's competitive edge in next-generation advanced process technology.