The leapfrog expansion of Taiwan Semiconductor Manufacturing (TSM)'s photonic integrated circuit (PIC) capacity is moving co-packaged optics (CPO) from the lab to mass production, opening a new growth window for the entire AI optical communications supply chain.

According to a report, brokerage analysts estimate that TSM's monthly PIC capacity will rapidly increase from the current approximately 500 wafers to 10,000 wafers in Q2 2026, 15,000 wafers in Q4 2026, and further to at least 25,000 wafers by 2028, representing a more than 30-fold expansion within three years.

Calculated at 648 dies per wafer, annualized PIC output will jump from about 4 million units to a maximum of nearly 194 million units, corresponding to an estimated actual optical engine shipment volume of up to 48.6 million units.

The direct beneficiaries of the capacity expansion are initially concentrated among leading customers. Analysts project that from 2026 to 2027, the primary mass production customers for TSM's COUPE platform will be dominated by Nvidia, Broadcom, and AMD. Following further capacity release in 2028, CPO projects from clients like MediaTek, Marvell, and Ayar Labs are also expected to be incorporated into the mass production platform. Concurrently, demand in downstream segments such as fiber array units (FAUs), lasers, optical testing, probe cards, test sockets, and automation equipment will also heat up in sync with the PIC volume ramp.

Behind the Capacity Surge: AI Computing Power Drives Optical Engine Demand

PIC is the core component of a CPO optical engine, responsible for converting, guiding, and coupling electrical and optical signals. As AI server cluster scales continue to expand and switch bandwidth evolves from 25T, 50T to 100T and 200T, the demand for optical engines rises correspondingly, making the progress of TSM's COUPE platform a key market focus.

Analysts point out that this round of PIC capacity expansion by TSM holds triple strategic significance. First, it marks the formal transition of CPO from experimental and small-batch verification phases into the mass production preparation stage. Second, the deep integration of silicon photonics with advanced packaging will enable COUPE, SoIC, and CoWoS to jointly form a more comprehensive AI photoelectric integration platform. Third, the PIC volume ramp will drive increased demand across the entire supporting supply chain, covering multiple links including FAU coupling, lasers, optical testing, and automation equipment.

Multiple Process Hurdles Remain, Volume Ramp Pace Still Uncertain

Despite the clear capacity expansion roadmap, analysts simultaneously caution that increased PIC capacity does not equate to an immediate, full-scale CPO volume ramp. After PIC wafers are completed, backend processes still need to sequentially pass through multiple stages including SoIC integration, photoelectric testing, optical engine packaging, FAU coupling, and system-level validation. Each of these stages constitutes a potential variable for yield and schedule.

Using analyst calculations as an example, under a scenario assuming a 50% SoIC yield, a monthly capacity of 10,000 wafers corresponds to an optical engine output of approximately 2 million units. Factoring in additional downstream assembly yield losses, the actual shipment volume would further narrow to about 390,000 units.

This indicates a significant yield loss between wafer capacity and final shipments. The yield ramp-up capability at each stage of the supply chain will, to a considerable extent, determine the actual pace and magnitude of the CPO volume ramp.