Taiwan Semiconductor Manufacturing Co's (TSMC) advanced packaging expansion is narrowing the supply-demand gap for CoWoS, but the supply chain bottleneck is shifting from memory to substrate materials.

Ho Jun, TSMC's vice president of advanced packaging and known as "CoWoS Man," stated that ABF substrate shortages could be second only to memory in the coming years, making it the next major constraint in the advanced packaging supply chain. Meanwhile, TSMC's CoWoS capacity has doubled annually for three consecutive years, with supply now "very close" to market demand, though it has not yet fully met it.

As CoWoS capacity gradually catches up with demand, the bottleneck in advanced packaging is moving upstream to materials. The increasing size and complexity of AI accelerators are further driving up demand for ABF substrates, making them a critical factor limiting advanced packaging expansion.

The narrowing CoWoS supply-demand gap and a 14x reticle size solution expected by 2029

Ho Jun noted that TSMC's CoWoS capacity has doubled annually for three straight years, and supply is now very close to market demand. The 5.5x reticle size CoWoS has entered mass production, with yields exceeding 98% across multiple AI client products. According to the technology roadmap, a 14x reticle size CoWoS is expected to debut before 2029.

As package sizes increase, the supply chain's demands on materials and manufacturing precision also rise. Ho Jun pointed out that when packages exceed 3x reticle size, all component quality standards must meet automotive-grade levels to keep failure rates within acceptable limits.

ABF substrates take over from memory as the new advanced packaging bottleneck

On the supply chain side, Ho Jun predicted that ABF substrate shortages will be second only to memory in the coming years, becoming the second-largest bottleneck in advanced packaging. Clients are already sourcing substrates from multiple suppliers to ensure supply, but differences in thermal and mechanical properties among suppliers are creating new challenges for manufacturing consistency.

At the same time, TSMC is accelerating its SoIC hybrid bonding technology. This technology achieved mass production with 6-micrometer pitch last year, with plans to further shrink it to 4.5 micrometers by 2029, and apply it to A14 chip stacking. Ho Jun stated that SoIC's interconnect density can reach 50 times that of traditional methods, with a roughly 5-fold improvement in energy efficiency.

Chiplet intelligent pairing and advanced packaging moves toward system-level coordination

As packaging complexity increases, TSMC is using Chiplet "intelligent pairing" technology to recombine chips with complementary performance. This reduces waste caused by individual chip performance variations, improving overall yield and effective output.

The role of interposers is also evolving from simple interconnection to integration, with future potential to house voltage regulators, capacitors, and silicon photonic devices. Meanwhile, TSMC is pushing for parallel development among clients, suppliers, and fabs, releasing system specification guidelines six quarters before mass production and requiring suppliers to station R&D teams near fabs to accelerate collaborative solutions to thermal, mechanical, and power issues.