The semiconductor industry is heating up once again.

As the global chip race approaches the 1nm milestone, Japan's "invisible champion" in semiconductor photomasks, Tekscend Photomask, has launched its IPO with a massive ¥156.6 billion, making it one of the most anticipated capital events on the Tokyo Stock Exchange in 2025.

Transitioning from the gravure printing division to a leading global photomask manufacturer, Tekscend Photomask not only holds the lifeblood of advanced processes at 2nm and below but has also established a triad of production capacity across Japan, the United States, and Europe, securing ties with top-tier clients. This IPO is a highlight of the Japanese capital market this year, raising ¥156.6 billion, placing it as the second-largest IPO in Japan for 2025.

**Successful IPO Launch** The second largest IPO in Japan for this year is set to take place.

Japanese semiconductor material manufacturer Tekscend Photomask has determined its initial public offering (IPO) issue price at the upper limit of the pricing range. The listing size ranks second among this year's IPOs in Japan.

According to records, the issuing guidance price for the company's shares was set between ¥2,900 and ¥3,000, with the final issuing price set at ¥3,000 per share. The IPO fundraising of ¥156.6 billion ranks only after the March IPO of JX Advanced Metals. This deal has attracted attention from institutional investors, including the Qatar Investment Authority, with insiders revealing that interest far surpasses the transaction's size itself.

Tekscend Photomask (テクセンド・フォトマスク) is a Tokyo-based global leader in photomask manufacturing, previously a division under Japan's Toppan Holdings. It became an independent entity through a spin-off in late 2021 and was officially renamed "Tekscend Photomask Corp." in November 2024. Toppan Holdings holds a 50.1% stake in the company, while the private equity firm Integral Corporation possesses 49.9%. The IPO on the Tokyo Stock Exchange is estimated to value the firm at around ¥300 billion, with Integral exiting by selling existing shares while Toppan retains control to maintain business synergy. Lead underwriters include Bank of America, Nomura, SMBC Nikko, and Morgan Stanley MUFG.

The company's core business spans semiconductor photomasks across process nodes from 90nm to 1nm, including high-end specifications such as EUV, OPC, and PSM, as well as nanopatterning components like nano-imprint templates and optical waveguides, serving various applications in logic, storage, and power devices. They operate eight factories across Japan, the United States, Europe, and Asia, making it the only photomask manufacturer with mass production bases on three continents to provide seamless "follow-the-sun" service. A major facility in Europe is located in Dresden, Germany, with plans to install the first Mycronic SLX1 laser writer at the Corbeil-Essonnes factory by the end of 2024, reducing high-end mask writing time from several days to 7-12 hours. They have also signed a five-year joint development agreement with IBM and imec to push forward the mass production of 2nm and even 1nm photomasks, with the target to achieve mass production of 2nm masks by fiscal year 2026. In November 2024, they will lead Europe with the installation of a multiple-beam electron beam mask writer (MBMW-ML2) to meet the complex graphic needs of GAA and CFET designs.

As one of the top three suppliers of semiconductor photomasks globally—behind Japan's HOYA and the U.S.'s Photronics—the company's main clients include IBM, GlobalFoundries, Taiwan Semiconductor Manufacturing (TSM), imec, and various domestic wafer manufacturers. They hold about 25% of the market share for advanced photomasks at 3nm and below and are the only manufacturer in Japan capable of mass production of EUV masks. Their projected fiscal year 2024 revenue is about ¥175 billion, with an operating profit margin of 18%. High-end masks (≤28nm) account for over 55% of their business, and they aim to raise $400-$500 million through the IPO to fund the development of 1nm level EUV masks, expand production capacity at their Dresden and Tokyo facilities, and repay acquisition loans. Strategically, they plan to complete the process validation for 1nm EUV masks by 2027 and achieve mass production by 2030 while concurrently developing companion masks for High-NA EUV. By the end of 2026, they aim to increase Dresden AMTC's capacity by 50% to meet local demand driven by the European Semiconductor Act 2.0, and within three years post-IPO, reduce their net debt ratio from the current 90% to below 40%, maintaining Toppan's controlling position. In summary, Tekscend Photomask is a leading global high-end photomask manufacturer that spun off from Toppan, leveraging cross-continental production capacity and advanced 2nm/1nm technologies as it races towards a Tokyo IPO, aiming to become the "invisible champion" in Japan's semiconductor equipment sector during the EUV era.

**An "Upstream Counterattack" is Underway** While TSM's factories in the U.S. and Germany are still in the planning stages, equipment is already being installed in Kumamoto Prefecture, Japan. In December 2024, TSM's JASM facility will launch the first batches of 28/22nm wafers with yield rates exceeding expectations, prompting Sony to announce domestic wafer rolling. Simultaneously, in Chitose, Hokkaido, the cleanroom lights of Rapidus are ablaze as 200 engineers from IBM collaborate with Japanese teams finalizing 2nm GAA transistor alignments. On the other side of Tokyo Bay, Shin-Etsu Chemical's new photoresist production line has completed sample delivery, and JSR announced plans to increase EUV photoresist capacity by 40% in 2025. From materials to manufacturing, Japan's semiconductor supply chain is experiencing a full-spectrum recovery, with simultaneous policy, capital, and geopolitical demands setting off an "upstream counterattack."

Prior to 2021, Japan's support for semiconductors was limited to "research funding." The 2022 implementation of the "Semiconductor Aid Act" enabled the government to directly subsidize 50% of investments in building new factory equipment, alongside a 10-year tax reduction. In 2024, further tax reforms introduced the "Domestic Production Promotion Tax," allowing the semiconductor, electric vehicle, and battery industries to enjoy a maximum tax credit of 20%. The passing of an amendment to the "Information Processing Promotion Law" in April 2025 permits the IPA (Information Processing Promotion Agency) to inject capital or convertible debt into semiconductor companies, similar to "Japan's National Big Fund." With fiscal policy, tax systems, and legislation working in tandem, Japan has established a regulatory framework to support its goal of reclaiming 10% of global semiconductor capacity within three years.

The establishment of Rapidus marks Japan's return to the semiconductor arena. This national team, formed by eight giants including Toyota, Sony, NTT, and SoftBank, aims to achieve mass production of 2nm logic chips by 2027. The government has pledged ¥1.72 trillion in subsidies, although this still falls short of the ¥5 trillion total investment. Behind this funding gap lies a precarious business model: Japan lacks fabless giants like Apple and Nvidia, requiring Rapidus to "create demand" by targeting custom chips for AI, automotive, and quantum communication markets. IBM provides GAA technology, imec shares EUV processes, and Hitachi Zosen is responsible for 3D packaging, forming a subtle "Japan-U.S.-Europe technology alliance." If successful, Japan will become the fourth economy globally, following the U.S., South Korea, and Taiwan, to achieve 2nm mass production capability.

While manufacturing efforts are grand, Japan's true "cash cows" lie upstream. Shin-Etsu Chemical, JSR, and Tokyo Ohka Kogyo control 70% of the global EUV photoresist market, and after export controls on China took effect in April 2025, prices have surged by 15%. In the equipment sector, Tokyo Electron commands a 90% market share in EUV coating and developing machines, while Advantest's EUV mask inspection systems have been integrated into Intel's 18A supply chain. In power semiconductors, Mitsubishi Electric, Toshiba, and Rohm collectively account for 30% of the global SiC device market, and Toyota's next-generation electric vehicles have confirmed the use of Japanese-made 6-inch SiC wafers. SUMCO's 12-inch silicon wafer orders stretch to 2026, with gross margins soaring to 35%, marking a ten-year high. The substantial upstream profits provide a cash flow boost for the cash-intensive downstream, creating a unique cycle of "using high margins to sustain low margins."

From 2020 to 2024, annual fixed asset investment in Japan's semiconductor industry grew by an average of 18%, far exceeding the manufacturing industry average of 4%. The funding sources present a "433" structure: 40% comes from government contributions, 30% from terminal industry capital like Toyota and Sony, and 30% from equipment and material companies from the U.S., South Korea, and Europe. ASML has established an EUV technology training center in Hokkaido, while Applied Materials has built a new ALD R&D line in Yokohama, both benefiting from subsidies equal to those enjoyed by Japanese firms. Foreign investments play both a role in filling technological gaps and undermining narratives of pure domestic production. However, Tokyo's policy circles do not shy away from admitting that, in an era of geopolitical shifts, "half cooperation, half competition" represents the most efficient supply chain strategy.

The revival of Japan's semiconductor sector does not mimic the "consumer electronics model" of twenty years ago but is instead tied to three new tracks: 1. Automotive—Toyota and Honda plan to raise the local content rate of autonomous driving chips from 15% to 60% by 2027 and procure 100% of power semiconductors domestically; 2. AI Edge Computing—NTT and NEC are jointly developing photonic computing chips, expected to go commercial in 2026; 3. Military—The 2025 revised "Defense Force Strengthening Plan" has listed "domestic high-end semiconductors" for military procurement for the first time, with Rapidus's first batch of 2nm capacity prioritized for AI-guided military weaponry demands. The combined market size of these three areas exceeds ¥80 trillion, providing a "warm-start" order pool for local wafer manufacturers.

Challenges related to funding gaps, customer uncertainty, and technological iterations loom overhead like three swords. If Rapidus cannot secure more than three Tier 1 clients with annual demands exceeding 500,000 wafers before 2026, the return period for its ¥5 trillion investment will extend to 15 years, far surpassing industry capital patience. Export controls could also have ramifications, as China accounts for 40% of Japan's semiconductor equipment exports. If China accelerates domestic replacements, revenues for Tokyo Electron and DISCO could drop by 8%-10% in the 2026 fiscal year. Nevertheless, Japan has placed its national fortunes on 2027: by then, Rapidus aims for 2nm mass production, TSM's JASM will expand phase II, Toyota's L4 autonomous vehicle regulation chips will begin mass production, and national defense AI chips will be delivered in bulk. If all four growth curves steeply rise simultaneously, Japan's global semiconductor market share could rebound from the current 6% to 12%, re-entering the ranks of "first-class players."

Japan's semiconductor journey from the "lost three decades" to the "upstream counterattack" has charted a unique path characterized by "using high margins to sustain low margins, trading policy for time, and forming alliances to expand markets." While it may struggle to replicate TSMC's scale myth, it provides a financial template for how traditional industrial nations can re-emerge. When high-end materials, precision equipment, and policy intent create a closed loop, latecomers too may find openings in the time window. Though the bell for 2027 has yet to toll, capital is already making pre-investments—over the next three years, Japan's semiconductor sector is likely to outperform the Nikkei 225, becoming a super β for global capital rebalancing.

**Challenges and Opportunities** Photomasks are compared to the "negatives" of chip manufacturing; the entity that masters the finest "negatives" holds the ticket to advanced processes.

Tekscend has signed a five-year joint development agreement with IBM and imec, committing to deliver 2nm test masks by the end of 2026 and mass production thereafter. Concurrently, the company is implementing the world's first 1nm electron beam writer in its Ibaraki factory, with plans for sample deliveries in 2027 and commercial use by 2030. In their prospectus, management has raised the revenue contribution target for EUV masks from 35% in 2024 to 55% by 2028, increasing profit margins by 6 percentage points. Should 1nm become a reality, the company will become the exclusive external photomask supplier for the joint development stage of TSM, Samsung, and Intel below 1nm, with the potential for a technical premium akin to ASML's surge during the 2017 EUV boom.

It is reported that 60% of the funds raised from the IPO will be used for expansion: new SLX1 laser writing platforms will be added at the Corbeil factory in France; a multiple-beam electron beam system will be introduced at the AMTC facility in Dresden, located adjacent to GlobalFoundries' 22FDX+ production line, minimizing logistics and data verification times; and the Round Rock facility in Texas is targeting defense and IDM clients.

Moreover, Tekscend views the 1nm photomask as its next major milestone, as outlined in its prospectus: the fiscal year 2026 will see 2nm test masks enter mass production, the first batch of 1nm trial pieces will be delivered to IBM and imec in 2027, and commercialization is expected by 2030, with the price per mask exceeding $800,000. To tackle this nanometer-level challenge, Tekscend plans to be the first to introduce the world's first multi-beam electron beam mask writer MBMW-ML2 at its Corbeil-Essonnes facility in November 2024, significantly compressing complex graphic writing time from several days to 7–12 hours, while also installing high numerical aperture EUV detection platforms at their Ibaraki base to ensure line width roughness is below 0.3nm. The five-year joint development agreement with IBM has specifically laid out the contract's focus on the 1nm node, with TSM, Samsung, and Intel expressing interest in early involvement in PDK design to secure priority access to external mask supplies. If the first batch of 1nm masks successfully passes customer risk trial production in the summer of 2027, Tekscend will become the world's only mass producer of 1nm masks as a third-party supplier, with the technical premium expected to mirror ASML's surge during the 2017 EUV boom, potentially leading to over 55% profit margins and a 45% upward valuation potential.

Tekscend Photomask's IPO also sends three significant investment signals to the semiconductor market:

First, bottleneck links in advanced processes are becoming new high grounds for capital investment. Photomasks are referred to as the "negatives" of chips, with a high technological barrier at 2nm/1nm, making the global mass producers fewer than three. Securing ¥156.6 billion in capital and a $2 billion valuation upon listing on the Tokyo Prime Market, with a $54 million cornerstone investment from Qatar's sovereign wealth fund, demonstrates institutional interest and a willingness to pay premiums for the "only external supplier of 1nm masks."

Second, Japan's "materials-equipment-manufacturing" closed loop is forming a high-margin cycle. The company's high-end mask revenue accounts for 55%, with an operating profit margin of 18%, far exceeding traditional wafer fabrication plants. The IPO funding is primarily allocated (60%) for expansions in Dresden and Tokyo, binding it to local supply chains for EUV photoresists, silicon wafers, and ALD equipment, thereby signaling the feasibility of a financial model rooted in "high upstream profitability supporting low downstream costs."

Third, amid geopolitical tech rivalries, a dual-localization premium reevaluation is underway for "technology + capacity." Tekscend's presence across factories in Asia, Europe, and North America allows it to benefit from subsidies under the U.S. CHIPS Act, the EU's Chips Act 2.0, and Japan's Semiconductor Aid Act, resulting in visibility of orders extending to 2027 for IBM and imec's 2nm at-risk mass production. The capital market has been illuminated by this insight: suppliers capable of cross-national capacity, able to absorb policy risks for their clients, stand to enjoy substantial valuation uplift and long-term contract bonuses, while segments such as photomasks, photoresists, EDA, and specialty gases may replicate ASML's valuation expansion trajectory during the 2017-2019 semiconductor supercycle.