Citi has significantly raised its price target for Micron Technology (MU.US) from $425 to $840, maintaining a "Buy" rating. The upgrade is based on expectations for price increases in Dynamic Random Access Memory (DRAM). Analysts stated, "We are raising our price target for Micron from $425 (5x our CY27 EPS) to $840 (8x our CY27 EPS) as we believe Micron will raise DRAM prices by more than 40% in the second half of the year, following peer Samsung's 100% price increase in the first half. Furthermore, we expect the DRAM upcycle to extend through calendar year 2027 and anticipate HBM [High Bandwidth Memory] prices will rise next year."

"Most DRAM price increases this year have focused on supply-demand imbalances in commodity or non-HBM DRAM. Although we believe the bit supply growth rate for DRAM is trending towards 30% by the end of 2026, based on recent expectations from equipment makers like Applied Materials (AMAT.US) for silicon systems sales growth exceeding 30%, additional new wafer capacity will still be needed to meet AI demand in 2027. Our forecasts for Micron align with Citi's research view that the average selling price (ASP) for DRAM will surge 200% year-over-year in 2026, while NAND ASP will rise 186% year-over-year."

SK Hynix and Samsung Electronics, both Korean companies, are among the world's largest memory chip manufacturers. SK Hynix is a major supplier of HBM chips to Nvidia. Samsung and Micron compete with SK Hynix in this segment. Citi analysts noted that HBM supply remains tight. They added that, given the 3-to-4 wafer conversion ratio and the profit margin differential between HBM and the commodity market, memory makers currently lack incentive to convert or add significant HBM capacity. The 3-to-4 wafer conversion ratio typically refers to the physical switch or processing cost comparison between 3-inch and 4-inch semiconductor substrates.

Analysts further stated that due to tight HBM capacity, they expect HBM pricing to remain elevated into 2027, and that memory manufacturers will be restrained in adding supply to prevent AI data centers from cutting HBM content next year. They mentioned that last week, in response to strong pricing, Cisco had already cut DRAM content by 50% across more than 20 items, including wireless products.

The manufacturing process for HBM is unique, involving the most complex advanced packaging, Through-Silicon Vias (TSV), and yield challenges the memory chip industry has faced to date. Strict cleanroom limitations and higher-level green energy efficiency requirements hinder rapid capacity expansion to meet surging prices. Traditionally, when prices become highly favorable for memory chip makers, supply typically increases quickly. However, the industry now faces numerous structural constraints—particularly as HBM, with its extremely complex manufacturing and packaging processes, increasingly absorbs capacity, while the supply elasticity for commodity DRAM/NAND remains insufficient, and AI-driven demand growth continues to outpace expectations.

In its first-quarter earnings call, Micron's management highlighted explosive demand for high-capacity data center SSDs for AI infrastructure, KV cache deployments, and PCIe Gen6 SSDs related to Nvidia AI computing infrastructure clusters. This indicates that AI-related memory chip demand is far broader than many Wall Street analysts had anticipated. Modern AI infrastructure not only consumes more HBM but also requires high-bandwidth DRAM, greater storage capacity, and high-speed SSD infrastructure to meet growing needs for retrieval and agentic AI workloads. Emerging AI applications, including robotics, multi-agent AI systems, and multimodal reasoning models, are also continuously creating new vectors of memory demand, suggesting that AI memory intensity may continue to grow exponentially even after initial AI deployments.

As Jeremy Werner, Senior Vice President and General Manager of Micron's Data Center Business Unit, revealed in a recent interview, the underlying driver of this cycle from an AI data center data flow engineering perspective is not simply that "AI needs more compute chips." Instead, the era of AI inference, dominated by AI agents like Claude Cowork and OpenClaw, has pushed memory/storage from a supporting component to a system bottleneck. AI training engineering relies more on large-scale parallel computing, while inference—especially for long-context, multi-turn conversations, and agentic AI workflows—requires continuous saving of KV Cache, context states, and intermediate results. When memory/storage space is insufficient, models must recompute historical states, leading to decreased GPU utilization and increased token generation costs.

Consequently, HBM, DDR5, LPDDR, enterprise SSDs, and even HDDs/data lakes are forming an "AI memory chain" from GPU-proximate to distant storage, determining an AI system's throughput, latency, concurrency, and per-token economics. This explains why storage and data storage stocks like Micron, Samsung, SK Hynix, SanDisk, and Western Digital are surging in tandem: demand is not concentrated solely on HBM but is spilling over across the entire chain of DRAM, NAND, SSDs, and HDDs along the AI server architecture.