Driven by the demand for AI computing power, the system area of chips using advanced packaging is continuously expanding. Traditional CoWoS technology, which utilizes a round silicon interposer, is becoming a bottleneck for large-sized AI chips due to limitations in reticle size and material properties.

Analyses from Huatai Securities clearly reveal an ongoing industry transformation: Taiwan Semiconductor Manufacturing is replacing conventional CoWoS technology with CoPoS technology, which uses a square glass substrate, to overcome the lateral development limits of advanced packaging. The core reason for this shift is that when chip area expands beyond 9.5 reticles, traditional CoWoS faces physical constraints like warping, high costs, and area limitations. CoPoS offers advantages including larger possible dimensions, lower signal loss, and a thermal expansion coefficient that can be matched to silicon. According to TrendForce, Taiwan Semiconductor Manufacturing began constructing a CoPoS pilot production line in Q1 2026, scheduled for completion in June. Apple has also started testing Samsung's glass substrates for AI packaging, indicating the industry's migration to CoPoS has substantially begun.

For investors, this signifies an accelerating formation of an incremental market driven by glass substrates, Through Glass Via technology, and Redistribution Layer equipment. While mass production by Taiwan Semiconductor Manufacturing might not occur until 2028, adoption in non-interposer applications like IC substrates and Co-Packaged Optics could progress faster than market expectations. With pilot lines currently under construction, related equipment and material suppliers are poised to benefit first.

The core driver is the increasing size of chips, which challenges round substrates. The roadmap presented by Taiwan Semiconductor Manufacturing at its 2026 North America Technology Symposium is key to understanding this trend. In 2024, its advanced packaging area was 3.3 reticles, increasing to 5.5 reticles by 2026 and reaching 9.5 reticles by 2027. The latest targets are 14 reticles by 2028 and over 40 reticles by 2029. A 14-reticle package area is approximately 12,000 square millimeters, equivalent to the size of two playing cards.

This demand for "large chips" comes directly from AI giants like NVIDIA, Google's TPU, and Apple's M-Ultra. However, Taiwan Semiconductor Manufacturing's current mainstream CoWoS-L solution, which uses local silicon bridges and organic RDL, faces significant challenges with warping, process complexity, and physical limits when dealing with such large areas. The solution is shifting from a round to a square format. CoPoS replaces the round silicon interposer with a square glass panel. The advantages of glass include: 1) potential for larger areas, unconstrained by round wafers; 2) extremely low signal loss, suitable for high frequencies; 3) a tunable thermal expansion coefficient that can match the chip, reducing warping; and 4) TGV aspect ratios up to 50:1, far exceeding Silicon Via's 10:1, enabling higher interconnection density.

The incremental opportunities lie primarily in TGV and RDL equipment, akin to "selling shovels" during a gold rush. CoPoS is an evolution of CoWoS towards a panel-based approach, necessitating a reshaping of the entire process chain. TGV technology creates the "nervous system" for the glass substrate. The process involves laser-induced modification, etching, cleaning, double-sided plating, annealing, and Chemical Mechanical Polishing. Ultrafast laser drilling equipment is critical here. Additionally, demand for panel-level horizontal plating equipment and CMP equipment will be significantly boosted. RDL technology lays down the "vascular system." As chip interconnection density increases, the number of RDL metal layers doubles, and copper bump pitch shrinks to 5 micrometers. This directly drives demand for direct-write lithography equipment, etching, thin-film deposition, and inspection tools. Automated Optical Inspection equipment is particularly crucial due to new yield challenges associated with glass substrate processes.

There are significant perception gaps in the current market view. Firstly, the application scope is broader than commonly assumed. While the market primarily focuses on CoPoS replacing CoWoS as an interposer, analysis indicates glass substrates' low loss and high density make them suitable for IC substrate replacement, Radio Frequency Fan-Out Panel-Level Packaging, and Co-Packaged Optics. Particularly for optical modules operating at 1.6T and above speeds, glass substrates are considered a core enabler for CPO due to superior high-frequency performance and optical waveguide integration capabilities. Secondly, the adoption timeline might be faster than anticipated. Although Taiwan Semiconductor Manufacturing's extension of the CoWoS interposer limit to 14 reticles might reduce the urgency for large-scale CoPoS production (TrendForce estimates mass production in 2028), progress in emerging applications like IC substrates and CPO could accelerate the commercial adoption of glass substrates. For instance, Intel introduced a sample using an 800-micrometer glass substrate for its Embedded Multi-die Interconnect Bridge packaging in early 2026.

CoPoS technology will reshape the advanced packaging value chain. Traditional packaging and testing houses may need to extend upstream into glass substrates and materials to master core processes like TGV and RDL. Conversely, panel manufacturers might leverage their glass substrate processing expertise to move downstream into packaging, leading to a reconfiguration of industry roles. From an investment perspective, three segments are positioned to benefit: First, glass substrate and upstream material suppliers, especially those with full TGV process capability and experience in mass-producing glass carriers. Second, core equipment providers, including suppliers of ultrafast laser drilling, panel-level plating, CMP planarization, direct-write lithography, and inspection equipment, where demand is expected to rise significantly. Third, packaging and testing companies with experience in Glass Chip-on-Film processes may expand into advanced TGV packaging. As Taiwan Semiconductor Manufacturing's pilot lines advance and customer validation proceeds, the growth potential in these areas is gradually materializing.