As transistor scaling faces diminishing returns, the industry is pivoting to Chiplet architectures and advanced packaging solutions to sustain performance gains. According to a research note from Guotai Haitong Securities Co., Ltd., the end of traditional cost scaling has made these approaches critical for balancing performance, cost, and yield.

The slowdown of Moore's Law has pushed the semiconductor industry to adopt Chiplet designs, where different functional blocks are split and then integrated using advanced packaging. This shift transforms packaging from a supporting process into a core platform for heterogeneous integration and system-level scaling. The growth of Chiplet counts, interconnect density, and system complexity is driving this evolution.

The market for advanced packaging is expanding rapidly, with 2.5D and 3D technologies serving as the primary growth drivers. As demand for HBM and logic chips increases, technologies like CoWoS-S are expected to evolve into CoWoS-L and EMIB. Meanwhile, HBM layers will transition from microbump connections to hybrid bonding, and emerging technologies like 3D Die-to-Die and 3D CBA DRAM are set to contribute additional growth in the coming years.

TSMC's CoWoS remains the dominant advanced packaging platform for AI chips, meeting the high-density integration needs of GPUs and HBM. However, capacity constraints and rising AI inference demand are creating opportunities for alternatives. Intel's EMIB technology, which offers lower cost and larger die sizes, is gaining external orders from ASIC makers, including Google, and is expected to become a significant supplement to CoWoS. Looking ahead, TSMC's CoPoS technology aims to address thermal and warpage issues by using rectangular substrates and glass substrates, potentially improving area utilization and reducing costs, with mass production expected in 2028.

Global semiconductor companies are increasing capital expenditure, with a notable shift toward back-end packaging and testing equipment. This benefits not only front-end tool giants but also mid- and back-end equipment suppliers. Bonding equipment providers like ASMPT and BE Semiconductor Industries N.V. will benefit from the rising adoption of thermal compression bonding and hybrid bonding, with the latter being a long-term trend for high-end packaging. Metrology and inspection equipment suppliers, including KLA and Onto, have significant opportunities as HBM layer counts increase, requiring more precise and frequent inspection steps. Test equipment providers such as TER and Advantest will also see growth from rising memory and logic test demand, as testing processes become more refined.

Key risks include weaker-than-expected AI demand, delays in new technology development and mass production, extended lead times for core equipment that could limit capacity expansion, and intensifying industry competition.