Cadence Design Systems Inc. has launched a Chiplet Spec-to-Packaged Parts ecosystem aimed at reducing engineering complexity and accelerating time to market for chiplet development in physical AI, data center, and high-performance computing applications. As part of this initiative, Cadence is collaborating with Samsung Foundry to create a silicon prototype demonstration of its Physical AI chiplet platform using the Samsung Foundry SF5A process. The ecosystem also includes key IP partners such as Arm, Arteris, eMemory, M31 Technology, Silicon Creations, and Trilinear Technologies, with silicon analytics support from proteanTecs. This collaboration is designed to help customers adopt advanced chiplet technologies more efficiently and reliably.

Disclaimer: This news brief was created by Public Technologies (PUBT) using generative artificial intelligence. While PUBT strives to provide accurate and timely information, this AI-generated content is for informational purposes only and should not be interpreted as financial, investment, or legal advice. Cadence Design Systems Inc. published the original content used to generate this news brief via Business Wire (Ref. ID: 20260106077060) on January 06, 2026, and is solely responsible for the information contained therein.