TSMC's Q2 2026 Earnings Call: Gross Margin of 67.7% Exceeds Guidance, Full-Year Capex Raised to $60-64 Billion

Stock News
Jul 16

Taiwan Semiconductor Manufacturing (TSM.US) held its FY26Q2 earnings conference call. The company announced a total cash dividend of TWD 4.67 trillion for 2025, a year-on-year increase of 28.6%, with a full-year cash dividend per share of TWD 18. For 2026, the cash dividend per share will rise to TWD 24, representing a further 33% increase year-on-year, with management committing to another increase in 2027.

Regarding performance guidance, revenue for Q3 2026 is forecasted to be between $44.6 billion and $45.8 billion, with the midpoint representing a 12% sequential increase and a 37% year-on-year increase. The gross margin is projected to be 65%–67%, and the operating margin is expected to be 56%–58%. The company raised its full-year 2026 revenue growth forecast in U.S. dollar terms to "slightly above 40%" (up from the previous guidance of over 30%).

On gross margins, the Q2 gross margin increased by 150 basis points sequentially to 67.7%, slightly exceeding guidance. The midpoint of the Q3 gross margin guide is 66%, down 1.7% sequentially, primarily due to a dilution of approximately 3–4% from the steep ramp of the 2nm process. The 2nm ramp in the second half of the year is expected to dilute gross margins by 3–4%. Ramping overseas fabs dilutes margins by 2%–3% in the early stages, expanding to 3%–4% in later stages.

Concerning capital expenditures, the company raised its full-year 2026 capital budget to $60–64 billion (up from the January guidance of approximately $52–56 billion and the April guidance of about $56 billion). Approximately 70%–80% of this is allocated to advanced process technologies, with about 10%–20% for advanced packaging, testing, and other areas. Q2 quarterly capital expenditure was approximately $15.7 billion. Cash and marketable securities at the end of the quarter totaled TWD 3.5 trillion (approximately $110 billion). Inventory days increased by 7 days sequentially to 87 days due to the N2 ramp.

Key Q&A Highlights

Q: Will this upturn cycle see a multi-year (26–28) capex guide similar to 2021?

A: There are no specific numbers to share at this time. We are investing capex this year for future business opportunities; whenever opportunities arise, we will not hesitate to invest. As stated in our prepared remarks, our confidence in the multi-year AI megatrend is very strong, and we are increasing capital expenditures and have raised this year's budget. Previously, we mentioned that capex over the next three years would be significantly higher than the past three years; now, the situation is that capex over the next three years will grow even more significantly compared to the past three years.

Q: After the additional $100 billion, cumulative investment in Arizona reaches approximately $265 billion. What are the capacity landing plans and timeline for Arizona in the coming years?

A: The timeline depends on market conditions. Given the current situation, the megatrend is very strong, which is why we announced additional investment in Arizona. How many fabs will be built? Many. Specifically, it is likely that approximately four additional fabs will be built (this includes previous funding arrangements).

Q: How do you respond to competition from foundry rivals like Samsung (with high profits from memory) and Intel (with U.S. policy support)? Some U.S. clients are engaging with these peers, and ASML announced EUV capacity expansion for 2028. Are you concerned about rivals securing more capacity to compete with you?

A: Yes, I have a competitor in Korea making a lot of money, and I envy them; another competitor in the U.S. has received strong support from the U.S. government—by the way, we have also received government support, just not publicly announced. But as we've said, there are no shortcuts. This means the semiconductor industry must return to fundamentals. We welcome and are grateful for government support, and money is certainly important. But the most important things are always technology, manufacturing, and customer trust. These fundamentals have never changed in my 37-40 year career, and this has always been TSMC's secret to winning business. From a competitive perspective, choosing a technology and ramping it to volume production is not like buying milk at 7-Eleven—you don't just see a better bottle of milk today and go to the next store, then switch again if you don't like it. You have to actually use it, validate it with test chips, collaborate, prepare capacity, and then ramp, which takes about five years.

Q: Given the strong signals from customers and their customers, and the raised full-year guide, will you revise the 5-year (semiconductor/AI) CAGR? Previously it was around the high 50% range. Also, with rising memory costs constituting a significant portion of AI capex, how should we view TSMC's contribution to AI-related growth?

A: If you read our information—we are continuously increasing investment and raising capex, all for good reasons. If you ask about the CAGR for AI, I won't give you a number, but the answer is stronger, stronger, and stronger. I'm not giving a number today because it is continuously rising, stronger than we previously indicated.

Q: Regarding competition in advanced packaging, especially EMT (Embedded/Interconnect-type packaging) gaining market attention, how is TSMC responding?

A: Our packaging capacity is very tight and has limited customer growth. Having some additional flexibility in the market actually helps TSMC's wafer business (which is the main part of TSMC's business). This technology reportedly looks good, and we hope it succeeds to take some of the load off TSMC's orders. We are currently working hard to close the gap between demand and capacity, so we welcome more alternatives to provide flexibility for customers.

Q: As a new technology, if issues arise after customer adoption, how would TSMC handle such special requests? Are there alternative solutions?

A: Our first priority is to support customer success. We are willing to do anything that helps our customers' businesses.

Q: When planning capacity expansion, besides demand from customers and their customers, do you also consider competitive pressure from rivals building capacity (as a market leader, long-term supply shortages are not ideal)? How long will it take to meet current demand? Furthermore, beyond chip shortages, there are issues like data center delays and power supply—how are these factored into the planning framework?

A: Competition is always the first consideration when evaluating any business; then we assess our position, using a combination of bottom-up and top-down methods to evaluate demand. This is the most difficult part of our daily work. We make many judgments and communicate more cautiously with customers and their customers (i.e., CSPs), gathering all demand inputs before making decisions. It's important to note: I believe every customer tells me the truth, but the sum of all customers' "truths" may not be the actual truth—because all CEOs are aggressive, that's their job. So we make very careful judgments, which may not be entirely correct, but because this involves large sums of money (this year's capex has been raised from about $52–56 billion to $60–64 billion and will continue to increase), we proceed very cautiously. We are also checking the progress of AI data centers—construction, site selection, demand, power, etc.—to ensure TSMC's chips are not piled up as inventory.

Q: Even with such a large-scale capacity expansion plan, do you still believe supply will remain tight through the end of next year?

A: You want a guarantee from me. I believe demand will be very strong from now until about 2029–2030. This trend is so robust, I think we are witnessing a brand new industry—I call it the AI industry, which is already deeply integrated into daily life and will affect automobiles, humanoid robots, and all industries. Given the scale of investment by everyone (including all CSPs), this is a very important new industry for the world, demand will persist, and its foundation is semiconductor chips, most of which are at TSMC.

Q: Regarding profitability: Long-term, foundry (especially advanced processes) profitability should be higher than memory. Now that TSMC is no longer the most profitable semiconductor manufacturer, does this mean current pressure to pass on costs and capture value from customers is less than a year ago?

A: Your question is essentially simple—what is TSMC's pricing strategy, what gross margin should it have? Of course, the higher the better. But we are partners; I have said many times that customers must succeed. I don't want to extract excessive value from the market; moreover, we are a company customers can trust. We won't suddenly raise prices 4x or 5x, as that would make it impossible for customers to survive. We earn the value we deserve and ensure profits and gross margins are sufficient to support long-term, sustainable expansion, which benefits both customers and TSMC. That is our philosophy. So, I do envy memory companies with 86% gross margins—I would be very happy with 68%. In summary, we are a highly trustworthy company.

Q: As AI demand significantly outpaces other end markets, the concentration ratio of the top five customers has reached a historical high. How do you view customer concentration risk?

A: This is not our concern. We are happy that customers are getting larger; some are growing very fast. And it's not simply a case of "big customers getting bigger"; actually, many new players are emerging in the AI industry.

Q: Your direct customers are providing financing/investment to their end customers to support AI demand. Would TSMC consider similar investment or financing arrangements for customers' customers (end customers)?

A: To answer directly: Each company has different considerations and strategies. So far, TSMC does not engage in such financial arrangements because our existing model of cooperation with current customers works smoothly and successfully.

Q: How will the additional $100 billion U.S. investment be distributed over the next 3–5 years, and what is the progress cadence?

A: We do have plans, but the progress and timeline largely depend on market conditions and customer demand. If you want a definitive schedule, I don't have one today, but we have plans and will push forward as fast as possible. (Addendum: Our new fabs and facilities in Taiwan will also proceed as quickly as possible, and the new fab in Japan will commence production as soon as possible, because the current supply-demand gap is large, and we are working to close it.)

Q: Regarding the computing portion within HPC—(CPO/co-packaged optics, etc.) platforms, when will they make a material revenue contribution?

A: Production has already begun and will ramp gradually over time. I believe AI data centers need to reduce power consumption and increase communication channel bandwidth, so demand for this technology will continue to grow and become quite significant in the coming years.

Q: Under the potential of Agentic AI and CPU growth, what is the growth potential and visibility for different AI chips (GPU accelerators vs. CPU/XPU)?

A: I cannot give very specific numbers, but I can share—they all use TSMC and the same advanced processes. We are working with customers to allocate wafer supply to balance the ratio of CPUs, GPUs, and XPUs.

Q: On advanced packaging, you previously announced a roadmap for 14x reticle size to enable larger AI packages, and recently demonstrated CoWoS glass substrate development in Japan. What is the current progress of new technologies like glass core, glass substrate, and glass carrier?

A: CoWoS remains mainstream today. We are developing alternatives to reduce costs and collaborating with substrate suppliers to help customers bring products to market. The pooling (related production lines) we announced several quarters ago is under construction and will take about another year to mature, after which we can enter volume production with customers.

Q: Can you quantify the sales growth outlook for the coming years? Also, please break down the key drivers for this capex increase and this year's demand—are they still mainly from cloud computing, or are they spreading to edge computing? Are there also factors like equipment supply chain price increases?

A: Because revenue corresponds to investment—we first forecast demand, make assessments, and then decide on capex. The coming years will be very good business for TSMC; that's all I can say. (On key drivers: Everything related to AI.)

Q: Backend packaging competition is intensifying (especially Intel's EMT). Are you concerned about the erosion of TSMC's overall foundry value from manufacturing to packaging?

A: Frontend wafer business and backend business are two different things; they are not the same. Moreover, our backend capacity is in a state of shortage, with an even larger gap, so I welcome competitors providing some flexibility for my customers to get frontend wafers packaged. This actually helps TSMC's wafer sales. That is our attitude.

Q: You previously mentioned High-NA equipment is too expensive. How do customers view the stitching challenges due to the smaller exposure field? Even with technical improvements, could this slow High-NA adoption?

A: You have a deep understanding of High-NA. Currently, its exposure field is only half the size, and we have factored this into manufacturing costs and other considerations. Whether we use it or not, High-NA is a very good tool with excellent performance. TSMC has clearly stated we are collaborating with ASML to make it more suitable for manufacturing in terms of cost and maturity. We will always comprehensively consider technical maturity and cost before deciding on adoption.

Q: The market generally assumes unconstrained demand for 3nm and below exceeds your supply capability by about 30%–50%. Is the actual gap larger?

A: We have no specific numbers to share. The gap is large.

Q: At a technology forum, you mentioned 2nm family capacity growing at about a 17% CAGR from '26–'28, and N3 & N5 at about a 25% CAGR. Do these assumptions still hold today? Have they changed over the past quarter?

A: The numbers on that chart we showed at the technology forum—they are bigger now. I'll just leave it at that.

Q: Advanced packaging capex has always been bundled with testing, mask making, etc., in the roughly 10%–20% of total capex. What is the actual percentage allocated to advanced packaging? How do you view the gap between packaging's revenue share and capex share? Should it be considered as a separate capex line item?

A: We work very hard to ensure capex numbers are accurate, but flexibility is needed between frontend and backend. Sometimes a bottleneck appears, and we invest more money to buy bottleneck equipment, sometimes in the frontend, sometimes in the backend. Long-term, the ratio is roughly the level I have always shared, with backend at about 10%–20%, a range that is already wide. Frankly, over time, as some customer products require more testing and testing demand rises, we will invest more capex in testers, packaging, or other areas, so we cannot specifically break down how much is invested in each area.

Q: Year-to-date, TSMC has raised its capex guide by nearly $10 billion. Where is the primary source of this upward revision? Compared to six months ago, is it from CPU/accelerators, memory makers, or backend capacity expansion changes?

A: The most important reason is continuously growing demand. We feel pressure from customers pushing (more accurately, working with TSMC) for capacity expansion; this is one of the main reasons. The second reason is inflation—we are now purchasing equipment at post-inflation prices.

Q: The market focuses on AI advanced processes, but mature processes also seem to be experiencing strong demand recovery and some supply tightness. How do you view the supply-demand dynamics and pricing for mature processes (with both AI spillover effects and heavy reliance on weak consumer demand)?

A: Mature processes cover many different segments. Only the parts related to AI are in shortage—the most important being Power Management ICs (PMICs), because all AI data centers require a lot of power management. These use mature process technologies and are indeed in shortage. Additionally, there is the sensor portion, as many sensors are needed to collect environmental information for AI data center analysis. Beyond that, as you pointed out, consumer product demand is starting to weaken, demand in other segments is not strong, and there is no widespread shortage.

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