For the past half-century, humanity has been obsessed with making things smaller. This was the only way to integrate more transistors onto a single chip. Shrinking transistors to 10 nanometers, 5 nanometers, and 3 nanometers defined semiconductor technology. But eventually, the laws of physics delivered a stark verdict: "You can't shrink any further." This forced a change in thinking. "If we can't shrink individual units, why not combine several to build something larger?" This question changed the game. Today, the core focus is no longer on microscopic circuits inside a chip, but on the "bridges" connecting chips and the "foundations" supporting them. The nanoscale war has ended; the micron-scale war has begun. And at the very center of this new battlefield stands a transparent material: glass.

Why can't chips get any larger? AI models are growing, and the number of transistors required on a chip is increasing accordingly. To accommodate more transistors, chip size must increase—but there is an unbreakable limit to chip size. Circuit patterns on chips are formed through photolithography, and the area a single exposure can cover is limited. This is the area limit of the photomask—with current technology, approximately 858 square millimeters. NVIDIA's GH100 chip already reaches 814 square millimeters, nearly touching this limit. Beyond size, there's another issue: yield. Imagine a large canvas divided into a grid. Each square represents a functional block. Now, flick a small paintbrush onto the canvas. Any square hit by a paint droplet is defective. If the squares are small, many blocks remain intact. But if the squares are large? Even a single droplet ruins an entire square. The larger the square, the faster the number of intact blocks drops. This is the yield problem. Chips can't get smaller, but they also can't get much larger. The monolithic chip is a dead end.

The industry's response has been to do the opposite: disaggregate and then reconnect. Imagine 3D printing Hogwarts Castle in one go. If one part fails, the entire piece is scrapped. But if you build with Lego bricks? A bad brick is simply replaced. Chiplets are like Lego bricks. They break a large chip into smaller components, manufactured separately and then assembled. Smaller chiplets have higher yields, naturally lowering costs. They aren't constrained by lithography limits. Even better, each chiplet can use a different process node—compute cores on cutting-edge 3nm, I/O circuits on cheaper 6nm. It's a rational choice, like using marble in the living room and brick in the warehouse. NVIDIA's Blackwell packages two near-limit-sized chips into a single GPU. Intel's Ponte Vecchio assembles 47 chiplets into one processor.

But this approach comes at a cost. Inside a single chip, components connect via internal wiring—fast, extensive, and low-power. Once a chip is disaggregated, communication that happened internally must move outside the chip. It's like a team moving from face-to-face meetings in one building to forced video calls across different offices. The quality of the video call determines the team's efficiency. If the connections between chiplets aren't as fast as the internal wiring they replace, there was no point in separating them. Simply making excellent chips is no longer enough. This era belongs to those who can connect them effectively.

The structure that stitches these small chiplets together resembles a Bacon & Egg McMuffin—minus the top bun. The bottom, English muffin-like structure is the substrate, the foundation supporting the entire assembly. It powers the chips, connects them to the outside world, and holds the package together. The bacon on top represents the chiplets—the GPU, HBM memory, and components that perform computations. When there was only one chip, you just placed the bacon on the muffin. But in the chiplet era, bacon slices need to communicate. So, a layer of egg is inserted between the muffin and the bacon: the interposer—a bridge enabling ultra-high-speed chip-to-chip connections. You may have heard the acronym CoWoS. It stands for Chip-on-Wafer-on-Substrate. 'C' is the chip (bacon), 'W' is the interposer (egg), and 'S' is the substrate (muffin). The name describes the structure. The key question for this architecture boils down to one decision: what materials are used for the egg and the muffin? This decision determines performance, cost, and how many AI chips the world can actually produce.

Organic substrates have reigned for 25 years. To understand this story, you must know who the king was. The vast majority of substrates today are organic—made from layers of resin and glass fiber. They are stable and inexpensive. Since replacing ceramic substrates in the late 1990s, organic substrates have silently been the semiconductor industry's foundation for a quarter-century. Twenty-five years is long enough for almost everything to change. During this time, transistor sizes shrank from hundreds of nanometers to 3nm, and chip computing power increased tens of thousands of times. But the substrate? It continued working silently on the same foundational material. AI shattered this calm.

To understand the problem, consider two tests a quality substrate material must pass. Test One: Withstand high heat. All materials expand when heated. When an AI accelerator consumes hundreds of watts and heats up, the chip (silicon) and the substrate beneath it expand—but at different rates. This difference in expansion rate is the Coefficient of Thermal Expansion (CTE). Organic substrates expand six to seven times more than silicon. For small packages, this difference is negligible. But at AI chip package sizes, this warping becomes severe. In the worst case, solder joints crack. Test Two: Protect signals. When electrical signals pass through the substrate, the material absorbs signal energy. Imagine a car driving on a dirt road. At low speeds, it's fine. But the ultra-high-frequency signals AI chips need become blurry and indistinct. Restoring blurred signals forces DSPs to work overtime, consuming power and generating heat, which further degrades signal quality—a vicious cycle. For 25 years, organic substrates passed these tests easily. Package sizes were small, speeds were slow. Facing AI chips, both tests are now failed simultaneously. The throne began to shake.

A "coup" began in Silicon Valley regarding the interposer—the layer directly connecting the chiplets. For this bridge that must transmit massive signals at high speed, organic materials were inadequate. In 2012, TSMC's answer was simple: "Let's build this bridge from silicon—the same material we make chips from." This is the core of CoWoS. Place a piece of silicon between the chiplets as the interposer. Using the same silicon minimizes CTE mismatch. Fabricated using semiconductor processes, it allows wiring finer than a fraction of a human hair. Without silicon interposers, today's AI chips would not exist. The problem is that silicon interposers are made on semiconductor wafers. They don't require the most advanced nodes but still consume TSMC's cleanroom space, wafer capacity, and packaging lines. Back to the McMuffin analogy: in a kitchen with only four stoves, frying the eggs (the interposer) requires two stoves. That leaves insufficient stoves to fry all the needed bacon (the chiplets). Building the bridge and making the chips require the same resources. This is the nature of the bottleneck. Cost is also high. A large silicon interposer can cost over $100, and the interposer alone may account for over half the total packaging cost. Packaging a top-tier AI chip is projected to cost around $1,300 by 2028. Size is another limitation. Silicon interposers are cut from round wafers, so yield logic applies. A larger interposer means fewer interposers per wafer and a higher defect rate. Silicon enabled what organics could not, but the price is too high. Amid exploding AI chip demand, the once-best bridge has become the biggest bottleneck.

Glass enters the challenge. Organic substrates are low-cost but hit a wall with AI chips. Silicon interposers are high-performance but consume packaging resources and are hard to scale. Between them lies a gap. This is where glass comes in. "Glass substrate" is a general term, but there are two distinct paths. Path One: Replace the interposer with glass. Use large-area glass processing equipment from the display industry to build the bridge layer currently occupied by silicon. In the McMuffin analogy, it's like replacing the egg with an ingredient that doesn't require heating. Freed-up heating equipment means more bacon (chiplets) can be made. Samsung is targeting this for 2028. Path Two: Replace the substrate with glass. This is a different approach—fundamentally breaking through the performance limits of organic substrates. While more expensive than organics, it offers value. Intel has invested over $1 billion on this path. It's the same "glass," but the problems being solved are different.

Glass can challenge because it delivers overwhelming results on the two tests where organics fail. CTE: Organic substrates: 17–20 ppm/°C. Silicon: ~3 ppm/°C. A six-to-seven-fold difference. Glass composition can be tuned to near 3 ppm/°C, meaning it can match silicon's CTE. This is a fundamental advantage. Package sizes impossible on organics become possible on glass. Signal Loss: If organics are a muddy road, glass is a pristine asphalt highway. Glass has over ten times lower signal loss than organics. Less signal loss means lighter burden on restoration circuits, lower power consumption, and less heat, breaking the vicious cycle. These two points alone are significant, but glass has two properties organics can never mimic. Its surface is extremely smooth. If an organic substrate's surface is like a dirt path, glass is like an ice rink. Hybrid bonding—an emerging technology that directly bonds copper pads without solder—relies on this smoothness. It can shrink the pitch between connections from tens of micrometers to under 10 micrometers, enabling orders of magnitude more connections in the same area. This is impossible on organics but feasible on glass. Glass is transparent; light passes through it, meaning optical waveguides can be embedded directly inside the substrate. Furthermore, with the rise of optical interconnects, their application is expanding from the chip surface into the substrate itself. In this world, electrical signals convert to light for transmission between chips—and glass is the foundational material to build it.

Of course, if glass were perfect, it would already dominate. First, the fundamental issue: glass can crack. During cutting, drilling, and handling, microscopic cracks form on the glass surface. As chips undergo tens of thousands of power cycles (expanding and contracting each time), these cracks can propagate rapidly, causing catastrophic failure. The industry is working on edge finishing and strengthening to suppress cracking, but long-term reliability data over thousands of thermal cycles is still lacking. Glass's thermal conductivity is two orders of magnitude lower than silicon's. Silicon is ~130–150 W/m·K; glass is ~1 W/m·K. But this weakness has an interesting twist. Remember glass's transparency—if waveguides are embedded and data travels as light, signals generate almost no heat passing through the substrate. Low thermal conductivity becomes less of a fatal flaw. Glass's weakness complements the advantages of optical interconnects. There's another paradox. Glass's property of not absorbing signals becomes an unexpected weakness for power delivery. In a noisy café, chatter from the next table is drowned out; but in an empty concert hall, a single cough echoes everywhere. A glass substrate is like that empty hall. Tiny noise from power delivery circuits isn't absorbed but reverberates, causing power fluctuations instead of smooth delivery. Reliability, thermal management, and power noise—glass faces three formidable challenges. Labs have proven glass's potential, but these hurdles must be overcome before mass production. One thing is certain: the blade once used to shrink transistors has dulled. In its place, the needle and thread connecting chips are becoming sharper. The substrate is no longer a simple plastic base; it is itself a vast circuit—a second semiconductor determining the entire system's performance ceiling. By 2028, glass is expected to be a core component of cutting-edge AI accelerators. Looking further—light can pass through glass, electrical signals can convert to light for chip-to-chip transmission—a new world awaits exploration. The possibility is proven. But significant obstacles remain between laboratory glass walls and factory production lines. Trillions of won are pouring in right now to overcome them. The real battle has just begun.

Glass leads in CTE matching and high-frequency signal characteristics. But in fine-pitch applications, it still lags far behind silicon. Its mass production yield is much lower than organic substrates, and cost is several times higher. With limited public production data, precise numbers are hard to pin down, but the industry's sober consensus is consistent: the economic gap remains too large. However, the most critical difference is that organic substrates have not yet hit a physical limit. This is starkly different from the clear obstacles faced by copper interconnects. It's time to ask the fundamental question again: Where are we going? Who will cross the mass production threshold first? Whose capital will be decisive? Right now, there appears to be no clear winner.

Intel's role in glass substrate technology development cannot be overlooked. For over a decade, Intel has invested over a billion dollars and holds nearly half the patents in this field. Their 2023 prototype stunned the industry. In January 2026, at NEPCON Japan, they showcased a Glass+EMIB demo product that operated without the micro-cracks common in glass cutting. On paper, Intel has the potential to become the Broadcom of the optical interconnect industry. But Broadcom's strength in optics isn't just patent count; it's the drive to manufacture directly, convince customers, and push the entire market paradigm. Intel's recent trajectory shows a different picture. In 2025, Duan Gang, a core figure in Intel's glass substrate project, moved to Samsung SEMCO. He holds over 500 patents and was named Intel's "Inventor of the Year" in 2024. He left Intel in June and joined Samsung Electro-Mechanics America in August. Multiple senior engineers reportedly followed. Around the same time, reports surfaced that Intel was in talks to license its glass substrate IP. Intel insists "R&D plans are unchanged," reiterated at the Intel Foundry Direct Connect in April 2025. But the loss of core talent and hesitation around licensing send different signals. Respected authority Professor Phil Garrou stated bluntly: "I do not expect Intel to have commercial glass substrate production before 2030." IP licensing isn't necessarily a losing proposition. Qualcomm, with its vast mobile patent portfolio, has sat on the mobile patent throne for decades, earning substantial royalties. But licensing technology and leading a market are two different things. Under CEO Cristiano Amon, Qualcomm is accelerating strategic prioritization. Whether glass substrates ultimately become a core business remains unclear.

What about Samsung? In terms of structural potential, it has built the most ambitious vertically integrated system among all players. SEMCO handles glass core substrate production. Samsung Display utilizes its large-area glass processing expertise from OLED lines for interposer solutions. Samsung Foundry handles final packaging integration. In the second half of 2024, a pilot line in Sejong began operations, and sampling to customers started in 2025. Samsung also signed an MOU with Sumitomo Chemical to plan a glass materials joint venture (a formal contract expected by 2026). Hiring Duan Gang aims to rapidly absorb Intel's decade of expertise. By February 2026, SEMCO had established a dedicated business unit. The issue lies with verified results. In November 2025, reports indicated Samsung's prototypes failed to meet customer specifications. Details are undisclosed, but it's clear: they haven't passed quality certification. The infrastructure is impressive, but "mass-production-grade quality" is not yet proven.

Absolics, a subsidiary of SKC, faces a different dilemma. They invested $600 million in a Georgia factory, receiving $175 million in government funding via the CHIPS Act and NAPMP. Factory—check. Funding—check. The only thing missing: a large customer to absorb significant volume. AMD is reportedly the most likely first customer, with approval expected in November 2025, but initial volumes are projected to be small. Worse, another potential customer, AWS, has indefinitely postponed quality testing. The initial mass production target of 2024-2025 has been delayed to 2027, and rumors suggest the company is conducting a full review of expansion plans. The player with the strongest patent portfolio has taken a half-step back in manufacturing. The player building the most complete vertical integration has not yet proven its quality. The player that built a giant fab first can't find a giant customer. The arsenal is full of weapons, but no leader has emerged to charge forward.

While the glass camp struggles with the mass production threshold, the organic camp hasn't been idle. Raja Koduri, former Intel/AMD GPU lead and current CEO of Oxmiq Labs, made incisive comments on X that cut to the heart of the current landscape. He stated: 1. The chiplet vs. large die yield problem is oversimplified... GPUs and other designs with many repetitive blocks have used redundancy and repair techniques for years to improve large die yield. These techniques apply to wafer-scale manufacturing. You need to design for it. 2. Don't abandon reliable organic substrates too soon; companies like Chipletz are working on promising approaches. 3. Micro-LED based interposers also look promising. 4. EMIB wasn't mentioned, and EMIB helps reduce the cost of using large silicon interposers. In silicon, the enemy of new physics is old physics... We underestimate the gains from iterating on old physics and overestimate our ability to master new physics for mass production. The old guard is also counterattacking.

Take Ajinomoto's ABF (Ajinomoto Build-up Film), the core insulating material for organic substrates. It holds over 95% global market share, a virtual monopoly. The current mainstream product has a line/space of about 10μm, but leading-edge processes reach 5-7μm. By 2025, the industry will formally enter the "sub-5μm race," with 3μm/3μm demonstrations in preparation. There is significant headroom for improvement before any physical limit is hit. Ajinomoto plans to increase capacity by 50% by 2030 with next-gen ABF products. This may not be disruptive innovation, but the power of continuous improvement, backed by 25 years of robust production infrastructure, should not be underestimated.

More aggressive breakthrough attempts are also underway. Chipletz, a fabless startup founded by former AMD engineers, introduced "Smart Substrate" technology, enabling high-density chip integration without a silicon interposer. Interestingly, SKC—the parent company of glass substrate firm Absolics—holds a 12% stake in Chipletz. This is a bet on emerging physics (glass) while hedging with traditional physics (organics).

Intel's EMIB (Embedded Multi-die Interconnect Bridge) is another powerful alternative not to be ignored. It embeds tiny silicon bridges into the organic substrate, applying silicon only precisely where chip-to-chip connection is needed. The bump pitch for chip interconnects has shrunk to 45μm—not directly comparable to glass TGV's 75-100μm, as they measure different bottlenecks. The direction is what's important. As Intel Foundry opens EMIB to external customers, Apple, Qualcomm, and MediaTek see it as a path around CoWoS bottlenecks. Even as Intel steps back from glass manufacturing, its organic-based solution is surprisingly expanding into new territory.

Blueprints for the more distant future also exist. New Silicon Corporation (NSC), a Singapore-based spin-off from the MIT SMART research consortium, has worked on monolithic integration of III-V compound semiconductors with silicon CMOS, recently extending this to optical interconnects. Reportedly, at the Asia Photonics Expo in February 2026, they achieved bandwidth density over 20 times higher than copper by combining silicon nitride waveguides with micro-LED arrays. While still in early lab stages, this reminds us that glass isn't the only contender for next-gen interconnect materials. Old physics doesn't die easily. For twenty-five years, it has battle-tested production infrastructure, tightly woven supply chains, and a mechanism for continuous improvement. For new physics to break through this line, benchmark performance alone is insufficient. It must prove its fundamental value: economic viability.

The biggest reason glass substrates are seen as a potential savior is the capacity bottleneck in TSMC's CoWoS production lines. With exploding AI chip sizes, the CoWoS lines producing silicon interposers simply can't meet demand. NVIDIA is estimated to consume over 60% of total capacity, with AMD, Broadcom, and Google splitting the remainder. This bottleneck naturally spawned the enticing narrative of the "Glass Substrate Opportunity." The logic is: the industry desperately needs an alternative packaging solution to escape TSMC's grip, and glass can fill the void. But consider the perspective from TSMC's side. Is this bottleneck a crisis they must solve at all costs? Or is it the most powerful weapon for controlling the entire market? The cruelty of a bottleneck is its duality. When the HBM market was supply-constrained, pricing power shifted entirely to suppliers, and memory makers reaped astronomical profits. TSMC is no different. The persistent CoWoS capacity shortage maximizes their pricing power and locks in major customers. NVIDIA's booking of substantial CoWoS capacity through 2027 is proof of this customer lock-in.

Of course, TSMC isn't idly watching the bottleneck. They are steadily advancing three strategies simultaneously. Step One is pure capacity expansion—the physical scaling of CoWoS output. Since 2025, equipment has been moving into the AP8 and Chiayi AP7 fabs, planning to increase monthly output by 60-70% above current levels by the end of 2026. The most straightforward, reliable plan: scale within the existing framework. Step Two is transformation. CoPoS—Chip-on-Panel-on-Substrate. This technology moves from printing interposers on round wafers to using 310x310mm square panels, minimizing waste at the edges, thus improving yield and capacity. Subsidiary VisEra Technologies will start a pilot line in 2026, beginning mass production by the end of 2028, with NVIDIA expected as the first customer. There's a crucial strategic intersection here: TSMC's roadmap explicitly leaves room for CoPoS to integrate glass substrates or silicon photonics in the future. This paves the way for TSMC to incorporate glass into its vast ecosystem. For independent glass substrate makers, this is a double-edged sword. If TSMC adopts glass, the market opens. But the fundamental raison d'être for the glass camp—"an alternative to bypass TSMC"—begins to erode. Step Three is deconstruction. The most disruptive move: CoWoP—Chip-on-Wafer-on-PCB. Led by SPIL, part of the ASE Group, with NVIDIA as a key partner, this aims to eliminate the ABF substrate layer entirely, placing the interposer directly onto a high-precision PCB. If successful, packaging costs would drop significantly. However, practical hurdles are immense. PCB fine-line capability must improve several-fold to reach ABF levels. Analysts like J.P. Morgan see low probability of near-term commercialization. But if this technology succeeds? The very concept of a "substrate" disappears. Glass, organics—all camps competing on it would instantly lose their reason for being. Expand, transform, deconstruct—TSMC has positioned itself meticulously for every possible scenario. Unless the glass camp closes the gap with overwhelming manufacturability, TSMC has little incentive to rush to resolve its key bottleneck.

At this point, you might feel lost in a thick fog. The glass camp is not yet organized. The organic camp's edge remains sharp. TSMC sits above, comfortably controlling the situation. Worse, academia is experimenting with third-party materials like silicon carbide and diamond CVD. Your confusion is normal. This isn't a clear shift like the optical transition. Multiple futures, based on different physics, are competing simultaneously. The key isn't predicting winners and losers too early, but interpreting signals at the inflection point.

Signals to interpret for the Glass Camp: 1. Absolics' first Purchase Order. If AMD's certification passes, this becomes the first-ever mass-production milestone for glass substrates—the transition from "experiment" to "industry." 2. Samsung's qualification hurdle. One company's success is just an experiment. Only when a second company gains approval does a full-fledged industry form. The completeness of the next-generation prototype—as indicated by the hiring of Duan Gang—is key.

Signals for the Organic Camp: 1. Ajinomoto ABF sub-5μm mass production. Once manufacturability of 3-4μm pitch is verified, the narrative of "the incumbent still dominates" will prevail. Glass R&D would be pushed into the 2030s. 2. Intel EMIB going mainstream. As Intel Foundry opens EMIB, and Apple, Qualcomm, and MediaTek watch closely as a path around CoWoS, a large tech company order would prove that high-density packaging on organics can integrate next-gen chips without glass. 3. The TSMC Platform: VisEra CoPoS panel pilot. If this panel line achieves stable capacity, TSMC secures a material-agnostic framework, allowing it to choose the substrate autonomously. Glass, silicon—any material can be used on the panel. For independent glass makers, this double-edged sword brings market opening but also the demise of the "bypass TSMC" survival premise. 4. CoWoP feasibility study. Low probability, high disruption. If this technology gains traction, the "substrate" concept itself vanishes. Glass, organics—all camps instantly lose their reason for being. 5. Interconnect standards like UCIe 3.0, SEMI 3D16. These won't make headlines, but invisible hands are building the industry's skeleton. The chosen interposer technology for next-gen chip interconnects will decide who is mainstream and who is niche.

Six signals, three camps racing. The side that receives the "achieved" signal first will determine where the fog finally clears.

On the battlefield of interposers and substrates, we are now in a fog. Glass substrates may ultimately win. Organic substrates may last another generation. Or the very concept of a substrate might disappear from the circuit diagram altogether. What decides the future is not pure technical superiority but brutal production yields, ruthless standardization battles, and TSMC's strategic calculus. If there is one undeniable truth, it is this: AI chips will only get larger, and current packaging capabilities cannot support this explosive growth. Physical limits are inevitably approaching. Change is imperative; only its form remains shrouded in fog. Absolics' first PO. The success of Samsung's next-gen prototype. The application of the VisEra panel pilot. ABF's breakthrough. Advances in PCB fine-pitch technology. We must connect these scattered data points and extract the key information. On a battlefield where the future is undecided, gaining an early insight into the approaching trend is the only strategy. The fog will eventually lift. When it does, the world will be split: some will have already occupied their positions, while others will still be searching for direction.