A long-standing approach to enhance chip performance has been to shrink transistor sizes and stack multiple device layers on a chip. However, as the pace of Moore's Law slows and devices approach physical limits, chip manufacturers face increasing challenges with further miniaturization.

Recently, a team from the University of Illinois Urbana-Champaign (UIUC) has developed a novel monolithic 3D silicon chip integration technique. Using an ultra-thin silicon nanomembrane less than 10nm thick in a process similar to roll-to-roll transfer, they have stacked high-performance silicon-based transistor layers under a thermal budget below 200°C.

The researchers achieved a three-layer stack, with each layer containing 625 transistors, demonstrating a yield between 98% and 100%. The performance is comparable to early commercial silicon MOSFETs while showing comprehensive manufacturing advantages over some alternative material approaches.

This technology offers a new solution to the physical limits of traditional 2D chip scaling, significantly increasing computational density through vertical stacking while potentially reducing power consumption. It holds promise for applications in AI, high-performance computing, and mainstream memory like DRAM.

Furthermore, the researchers noted that integrating silicon with other materials in monolithic 3D chips could open up entirely new application fields. For example, vertically stacking different types of single-crystal semiconductors might enable ultra-sensitive X-ray detector panels or compact multi-spectral imaging systems.

The related research paper, titled "Monolithic three-dimensional integration of silicon transistors," has been published in the journal Nature.

Key Technological Breakthrough

"For years, it was believed that manufacturing monolithic 3D chips required novel, rare materials like carbon nanotubes, metal-oxide semiconductors, or 2D semiconductors such as transition metal dichalcogenides," said Associate Professor Qing Cao of UIUC. "The fact that silicon can accomplish this task means the technology can be directly integrated into existing manufacturing processes, potentially accelerating its industrial adoption significantly."

The innovation lies in material design from the ground up. Instead of using standard processes, the researchers prepared junctionless transistors before the stacking process began. Unlike MOSFETs, which require a p-n junction, junctionless transistors have source, channel, and drain that are entirely p-type or n-type.

Manufacturing high-performance silicon devices typically requires high temperatures near 1,000°C. To avoid damaging existing structures, temperatures for subsequent layers must stay below 400°C after the first layer of circuitry and metal interconnects are completed. Junctionless transistors have less stringent high-temperature requirements; in this study, the needed temperature did not exceed 200°C.

Manufacturing Process and Advantages

From a process flow perspective, junctionless devices are relatively simpler, which helps reduce costs and improve yield. The team fabricated three layers of junctionless transistors on a 75mm silicon wafer, with each layer containing 625 transistors distributed over a 40x40 mm² area. These devices achieved yields between 98% and 100%, with performance matching that of standard silicon transistors fabricated at higher temperatures.

The new 3D chips were created using a wafer-scale roll-transfer printing process, layering uniformly doped single-crystal silicon films. These films are less than 10nm thick—over ten thousand times thinner than a human hair. Their ultra-thin and somewhat flexible nature allows them to conform to the topography of the underlying layer, helping to avoid issues like voids and warping common in rigid wafer bonding.

To ensure stable transfer and stacking of the silicon nanomembranes and prevent defects like cracks and wrinkles, the researchers made several engineering adjustments and optimizations to the process. These included adding surfactants in certain etching steps to reduce surface tension, incorporating polymer support layers for mechanical stability and surface protection, and applying uniform pressure during transfer using a roller lamination process.

Performance and Circuit Validation

The new monolithic 3D silicon chips demonstrate excellent performance. Measurement results show p-type transistors achieved a saturation current density above 650 µA/µm, with n-type reaching 550 µA/µm. The on/off ratio reached 10^6, and the subthreshold swing was between 80 and 120 mV/decade.

For circuit validation, the team placed p-type and n-type transistors on different layers and connected them via vertical metal interconnects. They constructed various logic gates and circuits using transistors distributed across the three layers of the 3D chip, including inverters, NAND gates, NOR gates, and a six-transistor SRAM cell.

Compared to planar layouts, the integration density of the 3D inverters and NAND gates increased by approximately 100%, and the memory cell density increased by about 300%.

This technology demonstrates a new possibility: vertical stacking does not require sacrificing transistor performance. Moreover, the roll-transfer equipment and process are fully compatible with existing production lines, providing a scalable path for extending Moore's Law based on single-crystal silicon.

Future Outlook and Industry Collaboration

Currently, this technology remains at the laboratory and small-batch prototype stage. As it scales towards mass production, it holds the potential to manufacture chips with higher density, greater energy efficiency, and shorter interconnects.

The research team is currently in discussions with companies including IBM, Intel, and TSMC regarding collaboration, with the hope of bringing this technology to practical application soon.