ASML (ASML.US) announced in July 2026 that Intel (INTC.US) has achieved high-volume manufacturing for specific Intel 18A process layers in certain Panther Lake products using the EXE series High-NA EUV equipment. The relevant High-NA layers have reached yield rates comparable to traditional NXE Low-NA EUV platforms. However, not the entire Intel 18A process uses High-NA, nor do all Panther Lake products; it is applied only to specific products and critical layers. This means Intel is not fully replacing Low-NA with High-NA but is instead validating data on exposure, overlay, equipment utilization, yield, and maintenance in a real mass-production environment.
As early as 2024, Intel and ASML completed the integration of the industry's first commercial High-NA EUV lithography system at their R&D center in Hillsboro, Oregon. Intel Foundry was also the first company to install and pass acceptance testing for the second-generation TWINSCAN EXE:5200B. Based on the TWINSCAN EXE:5000, the EXE:5200B uses an improved light source while enhancing output power and overlay accuracy.
Why is Intel the most aggressive? For Intel, the value of High-NA extends beyond simply reducing multiple patterning steps; it is about establishing a differentiated advantage for Intel 14A. This is a critical juncture for Intel Foundry. Recently, Intel Foundry secured orders from AMD, NVIDIA, and OpenAI, with successful bids for design solutions using its 18A and 14A process nodes. According to Wccftech, the yield rate for the 18A process has improved from 65% in the previous quarter to 85%, second only to TSMC's N2 (2nm) process at 90% yield, but far exceeding Samsung's SF2 process at 50-60% yield. High-NA is another powerful card for Intel. Intel's official roadmap has listed High-NA EUV as a key technology for Intel 14A, alongside PowerDirect backside power delivery. If Intel can master High-NA mass production first, it not only stands to improve transistor density and process complexity but also demonstrates to potential foundry customers its ability to take the lead in adopting the next-generation manufacturing platform. Therefore, Intel's strategy can be summarized as: first "train" with High-NA on a small portion of 18A mass production layers, then expand its use in 14A. This approach carries the highest cost and risk, but Intel needs technological leadership to buy time. For TSMC, High-NA is a cost choice; for Intel, it is more like a process proof it must win.
TSMC (TSM.US): Not Refusing, but No Immediate Need
TSMC's attitude toward High-NA is notably more restrained. Holding over 90% of the global advanced process foundry market share, with giants like Apple and NVIDIA in its supply chain, TSMC's top priority is "helping customers control costs, ensure yield, and deliver reliably." Therefore, from the 2nm (N2) and A16 to the A14 nodes, TSMC has clearly stated it does not require High-NA EUV. During the Q2 2026 earnings call, TSMC CEO C.C. Wei explicitly acknowledged that High-NA is a high-performance system but emphasized that the timing of its introduction depends on three conditions: technical capability, maturity, and cost reasonableness. Wei also specifically mentioned the half-field issue with High-NA equipment. Due to the anamorphic optical system, the single-exposure area of High-NA is only half that of traditional EUV, potentially requiring field stitching for large chips, which introduces challenges in overlay, yield, production efficiency, and design constraints. TSMC will factor all these elements into its manufacturing costs.
TSMC's confidence in temporarily not using High-NA also stems from the fact that A14 does not depend on it. How does TSMC's A14 achieve a 20% density increase without High-NA? TSMC distributes the resolution benefits High-NA could provide across multiple areas, including transistors, standard cells, masks, computational lithography, patterning, interconnects, and yield control, using a coordinated optimization approach to extend the life of 0.33 NA EUV. TSMC currently plans for A14 risk production in 2027 and mass production in 2028. Specifically, the primary gain for A14 comes from the transistor itself, using its second-generation nanosheet GAA transistor architecture. Compared to N2, A14's latest publicly stated goal is to offer a 10-15% performance increase at the same power or a 25-30% power reduction at the same performance, along with a near 20% logic density improvement. Another core technology disclosed for A14 is NanoFlex Pro. Through Design-Technology Co-Optimization (DTCO), it allows customers to make finer-grained choices for performance, power, and area across different functional blocks. TSMC Senior Vice President Kevin Zhang has explicitly stated that A14, through robust DTCO, significantly delays the need to rely on High-NA lithography.
Another factor is Low-NA multi-patterning. A14 will primarily use 0.33 NA EUV as its advanced lithography platform, continuing single-exposure on layers where possible, and adding necessary pattern splitting and multi-patterning only for the tightest, most complex critical layers. Masks are also crucial. TSMC is improving the manufacturability of 0.33 NA EUV at extreme patterns through more complex curvilinear masks, higher-resolution multi-electron beam writing, and finer mask corrections. In its annual report, TSMC disclosed its mask technology R&D for A14 and beyond includes: optimizing EUV mask substrate materials, improving resolution of multi-electron beam mask writers, optimizing mask manufacturing processes, improving critical dimension uniformity for curvilinear patterns, enhancing pattern fidelity and overlay accuracy, and using advanced electron beam inspection and repair to reduce mask defects. TSMC is also developing new EUV pellicles and mask substrates to improve yield, productivity, and equipment efficiency. TSMC's biggest advantage is precisely that it can afford to wait. It has the largest installed base of NXE systems, mature multi-patterning technology, high factory utilization, and stable customer demand, allowing it to avoid taking on High-NA depreciation early just to prove technological leadership. This does not mean TSMC rejects High-NA. TSMC started High-NA scanner lithography development in 2025, but it prefers to wait for conditions such as: further improvements in High-NA system throughput and availability; a mature ecosystem for photoresists, masks, inspection, and metrology; the cost savings from using High-NA exceeding the new depreciation costs; sufficient customer orders to amortize equipment costs; and resolution of the large chip half-field stitching problem.
Samsung: In a Waiting and Watching Phase
According to recent reports from TrendForce and Korean industry sources, Samsung has completed the installation of two ASML High-NA EUV systems (including the Twinscan EXE series) at its Hwaseong campus, with a total investment exceeding 1 trillion Korean Won (approximately $770 million USD). The first system was brought in for R&D testing in 2025, and the second was introduced in the first half of 2026. However, Samsung has not yet officially introduced them into any commercial production line, with mass production deployment currently in a state of delay and observation. The reports suggest Samsung's caution is not due to technical inadequacy but rather severe profit and loss statement pressure from its Foundry business. The unit price of a High-NA system is around $400 million USD, nearly double that of a traditional Low-NA EUV system. At a sensitive time when the foundry division has been under pressure since 2022 and is striving to break even, forcibly allocating the equipment to a commercial production line would immediately impact financial statements with massive hardware depreciation, factory maintenance, dedicated photomasks, and supporting R&D costs, potentially dragging the foundry business back into losses. Samsung's real challenges include: first, the number of customer contracts and order volume for advanced nodes (like 2nm GAA) still lag behind TSMC, making cost unacceptable if factory utilization is insufficient to amortize depreciation; second, while reports indicate significant progress in 2nm trial production yield, High-NA equipment cannot automatically solve nanometer-scale transistor architecture optimization, EDA software design ecosystem, or packaging issues; third, caught between Intel's high-profile introduction of High-NA for 18A/14A and TSMC's calculated waiting, a rash move by Samsung to mass-produce would only magnify fixed-cost risks. Therefore, Samsung's current more rational strategy is to "prepare but not use": keeping the purchased High-NA equipment in R&D and pilot lines for trial production and process characterization while strictly controlling commercial scale expansion. Samsung's most likely breakthrough remains in the 1.4nm (SF1.4) logic process and next-generation vertical channel transistor (VCT) advanced DRAM. Particularly in DRAM, as the pattern fineness of memory cells below 10nm approaches physical limits, the mask layers and process complexity of Low-NA multi-patterning increase sharply, making the economic value of High-NA EUV's single-exposure process simplification potentially more apparent than in logic foundry. However, Samsung has not yet formally announced a clear mass production timeline.
SK Hynix: Decisive for the Sake of HBM
In contrast to TSMC and Samsung's hesitation over the "half-field" issue and high costs, memory leader SK Hynix has taken a very decisive path regarding High-NA EUV. In September 2025, SK Hynix installed the industry's first mass-production High-NA EUV system for the memory sector at its M16 plant in Icheon. Unlike Intel's early trial production EXE:5000, SK Hynix introduced ASML's TWINSCAN EXE:5200B, a model truly designed for high-volume, mass production with a throughput of 175+ wafers per hour. SK Hynix plans to gradually integrate High-NA into the most advanced 0a nm class DRAM, and even future 3D DRAM production, around 2026-2027. For logic foundries like TSMC, large chips (like AI GPUs) face the "half-field" stitching problem with High-NA, which can actually reduce exposure efficiency. The physical characteristics of memory chips (DRAM) are distinctly different. This helps avoid the nightmare of multi-patterning: as DRAM technology advances to 1b, 1c, and 0a (sub-10nm) nodes, continuing with Low-NA EUV would require 3 or even 4 EUV multi-patterning steps, dramatically increasing mask layers, complicating processes, and causing yield to plummet. High-NA's single exposure can significantly simplify the process flow. Furthermore, it supports the core scaling needs of HBM: the technological iterations of HBM impose stringent demands on the capacitance density and channel width of the underlying DRAM cells. To maintain its dominant position in the NVIDIA supply chain, SK Hynix must rely on High-NA to achieve high integration and extreme performance at smaller dimensions.
ASML: The Biggest Winner
Regardless of the strategies employed by the foundries, ASML, the sole supplier, remains in a winning position. Taking its Q2 2026 financial report as an example: ASML posted net sales of €9.3 billion, a gross margin of 54.0%, and net income of €2.9 billion. Of the €6.6 billion in system sales, EUV equipment revenue was approximately €3.8 billion, non-EUV system revenue was about €2.8 billion, and the EUV revenue included only one High-NA system. This means that while High-NA has immense strategic value and a high unit price, it is not currently ASML's main source of revenue growth. ASML's true "three growth engines" are strong. The first is Low-NA EUV. ASML expects to deliver approximately 65 Low-NA EUV systems in 2026 and plans to increase Low-NA EUV capacity by another 30% in 2027, while already securing substantial orders for 2028. The reason is simple: 2nm, 3nm, HBM, advanced DRAM, and subsequent nodes still require a large number of 0.33 NA EUV systems. Even if some critical layers shift to High-NA, many other process layers will continue to use the NXE platform. The second engine is DUV immersion systems. ASML plans to increase DUV immersion system capacity by about 30% in 2027, with current capacity around 130 units, and is studying a further 30% capacity increase in 2028. This is because not all layers in advanced chips use EUV. Many non-critical layers, mature processes, analog chips, power devices, and advanced packaging still require DUV. The emergence of High-NA will not make DUV demand disappear; it may even grow alongside the overall capacity expansion of the foundries. The third engine, which many might not expect, is installed base services and upgrades. In Q2, ASML's installed base management revenue was nearly €2.8 billion. As the global installed base of EUV and DUV systems grows, services like maintenance, upgrades, light source power improvements, productivity enhancements, and computational lithography will generate recurring revenue. Regardless of whether a customer chooses to introduce High-NA early or continue relying on Low-NA multi-patterning, ASML secures revenue. ASML currently expects total net sales for 2026 to be between €43 billion and €45 billion, with a gross margin between 54% and 56%.
Final Thoughts
Regardless, the competition for High-NA EUV has moved from technical feasibility to economic feasibility. ASML's High-NA offers 8nm resolution, capable of printing features about 1.7 times smaller than 0.33 NA EUV, with a theoretical potential for a 2.9x increase in transistor density, and may replace some multi-patterning with single exposure. However, equipment price, half-field exposure, chip stitching, photoresists, masks, inspection equipment, throughput, and factory utilization all collectively determine whether it is more cost-effective than Low-NA. The eventual divergence among the four major players is a reflection of their respective commercial realities. Intel lacks time and is willing to pay a premium for "technology leadership." Samsung lacks foundry profit and dare not blindly expand fixed depreciation. TSMC lacks nothing in technology and comfortably calculates the best ROI. SK Hynix, for the absolute barrier of HBM, has taken the lead in the memory race. And ASML, securing orders from all, has become the biggest winner behind this divergence in strategy.