GF Securities released a research report stating that among future new technology directions, 4F2 and CBA technology similar to that used in 3D NAND fields are expected to become important breakthrough opportunities for further improving DRAM chip PPA performance. The development of emerging technologies such as 4F2 and CBA is expected to drive sustained growth in DRAM industry equipment demand. As emerging technology routes are explored and applied, equipment demand is anticipated to become more diversified, thereby opening up growth opportunities. Combined with the localization trend of related equipment, domestic semiconductor equipment growth potential is expected to expand further.

**4F2 and CBA Expected to Become Key Breakthrough Technologies for Further Improving DRAM Chip PPA**

Through analysis of current DRAM chip structural design and manufacturing processes, current DRAM chip upgrades at the wafer level are primarily achieved through two approaches: in-plane process scaling and architectural upgrades, continuously optimizing DRAM chip PPA performance. However, similar to how Moore's Law is gradually becoming ineffective or slowing down in logic processes, DRAM also faces bottlenecks in improvement magnitude and speed accompanying process scaling. Samsung, SK Hynix, and domestic memory manufacturers are actively exploring and applying architectural upgrades to achieve DRAM chip iteration. Among future new technology directions, 4F2 and CBA technology similar to that used in 3D NAND fields are expected to become important breakthrough opportunities for further improving DRAM chip PPA.

**4F2 is an Efficient Technology Route for Improving Storage Density**

4F2 structural layout means DRAM cells occupy 2F (where F represents feature size) in both wordline and bitline dimensions. Its implementation requires 3D vertical arrangement of DRAM transistors and capacitors, representing the most dense arrangement for in-plane DRAM cell layout. This is expected to reduce DRAM cell size by approximately 30% compared to 6F2, representing better area performance and storage density. Currently, the industry continues to advance development of 4F2-related DRAM technology. For example, Samsung reduces cell area by 30% through VCT technology that vertically arranges transistors, while SK Hynix plans to adopt 4F2 VG platform for sub-10nm nodes, combining hybrid bonding processes to achieve higher density and energy efficiency.

**CBA Technology is Key for Optimizing DRAM Chip System-Level Performance**

Referencing the architectural upgrade path of the Flash industry, future DRAM chips are also expected to achieve architectural upgrades through CBA technology. CBA technology separately manufactures storage array wafers and logic control unit wafers, then bonds the two wafers together through fusion bonding or hybrid bonding processes after manufacturing completion to achieve better overall system performance.

**DRAM Chip Architectural Optimization Expected to Diversify Equipment Demand, Opening Related Equipment Growth Opportunities**

Through analysis of related manufacturing processes, DRAM process scaling primarily relies on lithography process upgrades, while 4F2 and its underlying vertical transistor and capacitor structures rely more on deposition, etching, and other related processes beyond the original foundation. CBA technology also further increases demand for bonding, CMP, electroplating, and other processes beyond the original foundation. As the DRAM industry explores and applies emerging technology routes such as 4F2 and CBA, future equipment demand is expected to become more diversified, thereby opening growth opportunities for related equipment.

**Risk Warnings** Market demand may fall short of expectations, technology R&D may fall short of expectations, customer development may fall short of expectations.