Samsung Electronics unveiled its detailed technology roadmap for next-generation High Bandwidth Memory (HBM) and future storage architectures at SEMICON Taiwan 2026, showcasing advancements in HBM5, zHBM, and zNAND-O. This signals the South Korean memory giant's long-term strategic commitment to the AI infrastructure storage market.

Jangseok Choi, Corporate Vice President of Samsung's Memory Product Planning division, stated at the September 1 event that HBM5 targets double the performance of HBM4E, a 20% improvement in per-watt efficiency, and a 20% reduction in thermal resistance. Samsung had previously shared some related progress at Hot Chips 2026 in August.

The company also announced the development of an entirely new architecture called zHBM, targeting performance eight times that of HBM4E, with 3x better per-watt efficiency and a 75% to 90% reduction in thermal resistance.

This series of technological upgrades directly addresses the dual demands of high bandwidth and thermal management driven by the rapid expansion of AI accelerator computational power, providing significant reference value for the AI chip supply chain and related infrastructure investments.

HBM5: Process Upgrade to 2nm, Mass Production Expected in 2028

According to reports, HBM5 aims to double HBM4E's performance while delivering substantial improvements in power efficiency and thermal management. Samsung is upgrading the base die process for HBM5 from the 4nm node used in HBM4 and HBM4E to its self-developed 2nm node, marking a significant step forward in HBM process technology.

In terms of stacking configurations, Samsung is preparing 12-layer, 16-layer, and 20-layer DRAM stacks for HBM5 to accommodate varying capacity and performance requirements across different application scenarios. Volume production is expected to follow HBM4E, with timing projected around 2028.

The 20% thermal resistance reduction is particularly critical — as AI accelerator power consumption continues to climb, HBM's heat dissipation capability is increasingly becoming a system bottleneck, and this improvement helps maintain stable operation of high-performance computing systems.

zHBM: Disruptive Architecture with Memory Stacked Directly on Processors

Samsung positions zHBM as a fundamentally new architecture distinct from conventional HBM. While traditional HBM places memory alongside the AI accelerator (xPU), zHBM stacks memory directly on top of the processor, achieving higher bandwidth and better power efficiency by dramatically shortening data transmission paths.

Samsung's target for zHBM is performance reaching 8x that of HBM4E, 3x improvement in per-watt efficiency, and thermal resistance reduction between 75% and 90%. If this performance leap is realized, it would represent a fundamental breakthrough in bandwidth density and energy efficiency over existing HBM architectures.

zHBM is expected to launch after 2029, representing part of Samsung's longer-term technology reserve strategy.

zNAND-O: Approaching DRAM Speed with NAND Density

In the NAND storage segment, Samsung also introduced forward-looking technology directions. zNAND-O is planned to begin sampling in 2028, targeting storage density 10 times that of DRAM while achieving 7x the read bandwidth and power efficiency of NAND.

The design intent behind this technology is to satisfy the dual requirements of generative AI and large language models (LLMs) for "DRAM-level speed with NAND-level capacity" — as model sizes continue to expand, the trade-off between speed and capacity in existing storage architectures is increasingly becoming a bottleneck constraining AI inference and training efficiency.

CUBE Strategy: A Four-Dimensional Approach to Capacity, Utilization, Bandwidth, and Efficiency

At the Memory Executive Summit held alongside SEMICON Taiwan 2026, Samsung also systematically elaborated its "CUBE" strategic framework.

According to Jangseok Choi, this strategy revolves around four core priorities: Capacity, Utilization, Bandwidth, and Efficiency.

On capacity, Samsung plans to expand memory vertically, increasing storage density without enlarging the printed circuit board (PCB) footprint. Regarding utilization, the company is positioning the value of 3D memory beyond simple layer stacking, focusing on optimizing logic and memory architecture layouts to reduce latency. For bandwidth, Samsung plans to replace horizontal data paths with vertical high-speed channels to shorten inter-chip distances. On efficiency, the focus centers on power and thermal management, minimizing energy consumption per bit of data transferred while maximizing per-watt performance.

The introduction of the CUBE framework indicates that Samsung is attempting to coordinate the research direction of next-generation memory products through systematic architectural thinking, rather than pursuing breakthroughs solely on individual metrics.