Huawei proposed the "Tao (τ) Law" at the IEEE International Symposium on Circuits and Systems (ISCAS) 2026 in Shanghai on May 25, 2026. This law advocates replacing "geometric scaling" with "time (τ) scaling," utilizing innovative technologies like logic folding to continuously reduce signal propagation delay and increase transistor density, thereby exploring new pathways for the sustained evolution of semiconductors and electronic systems. The Tao Law is driving the semiconductor industry's evolution from process scaling towards design methodology, full-stack collaboration, and manufacturing data feedback loops. As the core industrial software foundation connecting chip design, manufacturing, packaging, and system optimization, domestic Electronic Design Automation (EDA) tools are expected to see their strategic value continuously rise.

As process node benefits diminish, design collaboration emerges as the new focus for semiconductors. Huawei's introduction of the Tao Law essentially shifts the semiconductor evolution logic from relying solely on geometric process scaling to a comprehensive optimization centered on time constants, signal propagation delays, and system performance, against the backdrop of Moore's Law reaching its marginal limits. Huawei pointed out that Moore's Law, which has dominated the semiconductor industry for over half a century, is now facing dual challenges from physical limits and economic efficiency. The slowdown in transistor geometric scaling and the fading of transistor cost benefits have become common industry challenges. Huawei disclosed that the Tao Law establishes a multi-level collaborative optimization system spanning devices, circuits, chips, and systems. At the circuit level, logic folding breaks through the physical boundaries of traditional planar layouts, shortens critical path routing lengths, and reduces the resistance and capacitive load on signal propagation. The core contradiction in the semiconductor industry may shift from "whether we can continue to shrink processes" to "whether we can use EDA and design methodologies to unlock the potential of existing processes and system architectures."

The emphasis on full-stack collaboration is increasing, driving a systemic upgrade for the EDA toolchain. The Tao Law emphasizes full-stack hardware-software-chip co-design of "software, architecture, and chips," and at the system level, it reconstructs computing system interconnect protocols through the Lingqu Bus to reduce system communication latency. For the EDA segment, this means the toolchain is no longer just for circuit drawing, layout design, and back-end verification. It must further integrate key processes such as device modeling, PDK construction, circuit simulation, parasitic parameter extraction, timing and power analysis, physical verification, advanced packaging, and system-level collaborative optimization. The website of Empyrean Technology shows that its EDA products cover areas including full-custom design platforms, digital circuit design, wafer manufacturing, advanced packaging, and 3DIC design, aligning with the industry trend of complex chip design moving from point tools to full-flow platforms. The Tao Law is expected to promote the upgrade of domestic EDA from "point tool replacement" to a "full-flow, cross-level, strongly collaborative" industrial software foundation.

Mass production validation opens new opportunities, moving domestic EDA from substitution to innovation. Huawei stated that over the past six years, it has designed and mass-produced 381 chips based on the Tao Law. Among them, the upcoming Kirin chipset, set for release in autumn 2026, will be the first to adopt logic folding technology, delivering a significant performance boost. Unlike mere conceptual announcements, the mass production of 381 chips indicates this pathway has entered the engineering validation phase. For the EDA industry, new architectures, methodologies, and design constraints will generate substantial demand for localized tool adaptation, design-manufacturing collaboration, and system-level verification. State Council policies clearly identify the integrated circuit and software industries as the core of the information industry, proposing further optimization of the industrial development environment and enhancing innovation capability and development quality. Shanghai's policies also include implementing special actions for EDA ecosystem construction, supporting breakthroughs in full-flow EDA tools, the development of open EDA cloud platforms, and procurement of independently secure and controllable EDA tools. Domestic EDA is expected to progress from "substituting for foreign tools" to a stage of "collaborative innovation oriented towards domestic processes, domestic architectures, and domestic systems." Platform vendors with capabilities in process collaboration, manufacturing data feedback loops, and established customer ecosystems are likely to benefit first.

Risks include slower-than-expected engineering progress on new semiconductor pathways, slower-than-expected validation and customer adoption of domestic EDA products, fluctuations in capital expenditure from downstream wafer foundries and chip designers, and risks related to the international trade environment and supply chain disruptions.