IT之家 4 月 13 日消息，韩媒《釜山日报》当地时间今日报道称，尽管三星电子的 2nm 工艺制程良率当前达到了 55% 上下，但该水平不仅落后于台积电约一成，另一方面也没有达到竞争重要 Fabless 企业代工订单所需的水平。
IT之家注：
媒体报道通常仅提到良率而未给出对应的芯片面积，这导致良率数据的价值与可比性不足。
举个较极端的例子，在 100mm² 的芯片（移动端 SoC 级）上取得 90% 良率的难度远小于在 600mm² 芯片（旗舰 AI XPU 级）上实现同等良率。
业界人士指出，如果再考虑性能分级和后端封测流程的损失，以最终成品计三星电子的 2nm 良率将只剩下 40%。这意味着该节点当前仍未成熟，无法稳定交付，且实际价格竞争力也相对不足，仅有个别成本敏感的小型企业会选择尝试。
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